![background image](http://html1.mh-extra.com/html/omron/sysmac-cs1d-cpu/sysmac-cs1d-cpu_reference-manual_7422681011.webp)
972
Basic I/O Unit Instructions
Section 3-23
shown below, so that IOWR(223) will be executed with each cycle until the
writing operation is executed.
When the input condition is met, self maintenance is performed by output A
and IOWR(223) is executed with each cycle until the Equals Flag turns ON.
When the writing is completed and the Equals Flag turns ON, output B turns
ON and the self maintenance is cleared.
Be sure to place condition flags directly after IOWR(223) instructions, and not
after any other instructions. If a condition flag is placed after another instruc-
tion, it will be affected by the execution results of that instruction.
IOWR(223) can be used in an interrupt task, which allows high-speed pro-
cessing of specific I/O data with an interrupt. If IOWR(223) is used in an inter-
rupt task, always disable cyclic refreshing of the specified Special I/O Unit by
turning ON the corresponding Special I/O Unit Cyclic Refreshing Disable Bit in
the PLC Setup.
When cyclic refreshing of the specified Special I/O Unit is enabled in the PLC
Setup (the corresponding Special I/O Unit Cyclic Refreshing Disable Bit is
OFF), a non-fatal Duplicate Refresh Error will occur and the Interrupt Task
Error Flag (A40213) will go ON in the following cases.
• Words allocated to the same Special I/O Unit were already refreshed by
IORF(097) or FIORF(225) (CJ1-H-R CPU Units only).
• Words allocated to the same Special I/O Unit were read or written by
IORD(222) or IOWR(223).
B
IOWR
C
S
=
B
D
A
A
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...