GD32F10x User Manual
634
The normal bit time from the CAN protocol has three segments as follows:
Synchronization segment (SYNC_SEG)
: a bit change is expected to occur within this time
segment. It has a fixed length of one time quantum (
1 × 𝑡
𝑞
).
Bit segment 1 (BS1)
: It defines the location of the sample point. It includes the Propagation
delay segment and Phase buffer segment 1 in the CAN standard. Its duration is
programmable from 1 to 16 time quanta but it may be automatically lengthened to
compensate for positive phase drifts due to different frequency of the various nodes of the
network.
Bit segment 2 (BS2)
: It defines the location of the transmit point. It represents the Phase
buffer segment 2 in the CAN standard. Its duration is programmable from 1 to 8 time quanta
but it may also be automatically shortened to compensate for negative phase drifts.
The bit time is shown as in the
Figure 21-11. The bit time
Sync
segment
Propagation
delay
segment
Phase buffer
segment 1
Phase buffer
segment2
Normal Bit Time
CAN
protocol
SYNG_SEG
BIT SEGMENT 1(BS1)
BIT SEGMENT 2(BS2)
CAN
The resynchronization Jump Width (SJW): it can be lengthened or shortened to compensate
for the Synchronization error of the CAN network node. It is programmable from 1 to 4 time
quanta.
A valid edge is defined as the first toggle in a bit time from dominant to recessive bus level
before the controller sends a recessive bit.
If a valid edge is detected in BS1, not in SYNC_SEG, BS1 is added up to SJW maximumly,
so that the sample point is delayed.
Conversely, if a valid edge is detected in BS2, not in SYNC_SEG, BS2 is cut down to SJW at
most, so that the transmit point is moved earlier.
Baud rate
The clock of the CAN derives from the APB1 bus. The CAN calculates its baud rate as follow:
𝐵𝑎𝑢𝑑𝑅𝑎𝑡𝑒 =
1
𝑁𝑜𝑟𝑚𝑎𝑙 𝐵𝑖𝑡 𝑇𝑖𝑚𝑒
(21-1)
𝑁𝑜𝑟𝑚𝑎𝑙 𝐵𝑖𝑡 𝑇𝑖𝑚𝑒 = 𝑡
𝑆𝑌𝑁𝐶_𝑆𝐸𝐺
+ 𝑡
𝐵𝑆1
+ 𝑡
𝐵𝑆2
(21-2)
with:
Summary of Contents for GD32F10 Series
Page 63: ...GD32F10x User Manual 63 programmed during the chip production ...
Page 117: ...GD32F10x User Manual 117 010 1 0 011 0 9 ...
Page 416: ...GD32F10x User Manual 416 shadow register updates every update event ...
Page 427: ...GD32F10x User Manual 427 value ...
Page 518: ...GD32F10x User Manual 518 These bits are not used in SPI mode ...