GigaDevice Semiconductor GD32F10 Series, User Manual

Page: 133 / 853

GD32F10x User Manual
133
1: Enabled DMA0 clock
5.6.7.
APB2 enable register (RCU_APB2EN)
Address offset: 0x18
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
USART0
EN
TIMER7E
N
SPI0EN
TIMER0E
N
ADC1EN ADC0EN PGEN PFEN PEEN PDEN PCEN PBEN PAEN Reserved AFEN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits Fields Descriptions
31:15 Reserved Must be kept at reset value
14 USART0EN USART0 clock enable
This bit is set and reset by software.
0: Disabled USART0 clock
1: Enabled USART0 clock
13 TIMER7EN TIMER7 clock enable
This bit is set and reset by software.
0: Disabled TIMER7 clock
1: Enabled TIMER7 clock
12 SPI0EN SPI0 clock enable
This bit is set and reset by software.
0: Disabled SPI0 clock
1: Enabled SPI0 clock
11 TIMER0EN TIMER0 clock enable
This bit is set and reset by software.
0: Disabled TIMER0 clock
1: Enabled TIMER0 clock
10 ADC1EN ADC1 clock enable
This bit is set and reset by software.
0: Disabled ADC1 clock
1: Enabled ADC1 clock
9 ADC0EN ADC0 clock enable
This bit is set and reset by software.