GD32F10x User Manual
169
7.5.3.
Port input status register (GPIOx_ISTAT, x=A..G)
Address offset: 0x08
Reset value: 0x0000 XXXX
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10
ISTAT 9
ISTAT 8
ISTAT 7
ISTAT 6
ISTAT 5
ISTAT 4
ISTAT 3
ISTAT 2
ISTAT 1
ISTAT 0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:0
ISTATy
Port input status(y=0..15)
These bits are set and cleared by hardware
0: Input signal low
1: Input signal high
7.5.4.
Port output control register (GPIOx_OCTL, x=A..G)
Address offset: 0x0C
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OCTL15
OCTL14
OCTL13
OCTL12
OCTL11
OCTL10
OCTL9
OCTL8
OCTL7
OCTL6
OCTL5
OCTL4
OCTL3
OCTL2
OCTL1
OCTL0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:0
OCTLy
Port output control(y=0..15)
These bits are set and cleared by software
0: Pin output low
1: Pin output high
Summary of Contents for GD32F10 Series
Page 63: ...GD32F10x User Manual 63 programmed during the chip production ...
Page 117: ...GD32F10x User Manual 117 010 1 0 011 0 9 ...
Page 416: ...GD32F10x User Manual 416 shadow register updates every update event ...
Page 427: ...GD32F10x User Manual 427 value ...
Page 518: ...GD32F10x User Manual 518 These bits are not used in SPI mode ...