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GigaDevice Semiconductor GD32F10 Series, User Manual

The GigaDevice Semiconductor GD32F10 Series is a cutting-edge product that offers exceptional performance and versatility. To make the most of this innovative device, it is essential to have the User Manual. You can easily download the comprehensive manual for free from manualshive.com, ensuring you unlock its full potential.

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GD32F10x User Manual

 

457

 

 

17.3.4. 

Clock synchronization 

Two  masters  can  begin  transmitting  on  a  free  bus  at  the  same  time  and  there  must  be  a 
method for deciding which master takes control of the bus and completes its transmission. 
This is done by clock synchronization and bus arbitration. In a single master system, clock 
synchronization and bus arbitration are unnecessary. 

Clock synchronization is performed using the wired-AND connection of I2C interfaces to the 
SCL  line. This means that  a HIGH to LOW transition  on the SCL  line causes the masters 
concerned to start counting their LOW period and, once a master clock has gone LOW, it 
holds the SCL line in that state until the clock HIGH state is reached (see

 Figure 17-4. Clock 

synchronization

). However, if another clock is still within its LOW period, the LOW to HIGH 

transition of this clock may not change the state of the SCL line. The SCL line is therefore 
held LOW by the master with the longest LOW period. Masters with shorter LOW period enter 
a HIGH wait-state during this time. 

Figure 17-4. Clock synchronization 

CLK1

CLK2

SCL

 

17.3.5. 

Arbitration 

Arbitration, like synchronization, is part of the protocol where more than one master is used 
in the system. Slaves are not involved in the arbitration procedure. 

A master may start a transfer only if the bus is free. Two masters may generate a START 
signal within the minimum hold time of the START signal which results in a valid START signal 
on  the  bus.  Arbitration  is  then  required  to  determine  which  master  will  complete  its 
transmission. 

Arbitration  proceeds  bit  by  bit.  During  every  bit,  while  SCL  is  HIGH,  each  master  checks 
whether the SDA level matches what it has been sent. This process may take many bits. Two 
masters can even complete an entire transmission without error, as long as the transmissions 
are identical. The first time a master tries to send a HIGH, but detects that the SDA level is 
LOW, then the master knows that it has lost the arbitration and turns off its SDA output driver. 
The other master goes on to complete its transmission. 

Summary of Contents for GD32F10 Series

Page 1: ...GigaDevice Semiconductor Inc GD32F10x Arm Cortex M3 32 bit MCU User Manual Revision 2 6 Jun 2022 ...

Page 2: ...ts 42 1 6 System configuration registers 43 2 Flash memory controller FMC 44 2 1 Overview 44 2 2 Characteristics 44 2 3 Function overview 44 2 3 1 Flash memory architecture 44 2 3 2 Read operations 45 2 3 3 Unlock the FMC_CTLx registers 46 2 3 4 Page erase 46 2 3 5 Mass erase 47 2 3 6 Main flash programming 49 2 3 7 Option bytes Erase 50 2 3 8 Option bytes modify 51 2 3 9 Option bytes description ...

Page 3: ... 64 3 3 1 Backup domain 65 3 3 2 VDD VDDA power domain 66 3 3 3 1 2V power domain 68 3 3 4 Power saving modes 68 3 4 Register definition 71 3 4 1 Control register PMU_CTL 71 3 4 2 Control and status register PMU_CS 72 4 Backup registers BKP 74 4 1 Overview 74 4 2 Characteristics 74 4 3 Function overview 74 4 3 1 RTC clock calibration 74 4 3 2 Tamper detection 75 4 4 Register definition 76 4 4 1 Ba...

Page 4: ...lock control unit RCU 110 5 4 Reset control unit RCTL 110 5 4 1 Overview 110 5 4 2 Function overview 110 5 5 Clock control unit CCTL 111 5 5 1 Overview 111 5 5 2 Characteristics 113 5 5 3 Function overview 113 5 6 Register definition 118 5 6 1 Control register RCU_CTL 118 5 6 2 Clock configuration register 0 RCU_CFG0 120 5 6 3 Clock interrupt register RCU_INT 123 5 6 4 APB2 reset register RCU_APB2...

Page 5: ... 3 1 GPIO pin configuration 154 7 3 2 External interrupt event lines 155 7 3 3 Alternate functions AF 155 7 3 4 Input configuration 155 7 3 5 Output configuration 155 7 3 6 Analog configuration 156 7 3 7 Alternate function AF configuration 156 7 3 8 IO pin function selection 157 7 3 9 GPIO locking function 158 7 4 Remapping function I O and debug configuration 158 7 4 1 Introduction 158 7 4 2 Main...

Page 6: ...er 1 AFIO_PCF1 183 8 Cyclic redundancy checks management unit CRC 185 8 1 Overview 185 8 2 Characteristics 185 8 3 Function overview 186 8 4 Register definition 187 8 4 1 Data register CRC_DATA 187 8 4 2 Free data register CRC_FDATA 187 8 4 3 Control register CRC_CTL 188 9 Direct memory access controller DMA 189 9 1 Overview 189 9 2 Characteristics 189 9 3 Block diagram 190 9 4 Function overview 1...

Page 7: ... 4 1 ID code register DBG_ID 207 10 4 2 Control register DBG_CTL 207 11 Analog to digital converter ADC 211 11 1 Overview 211 11 2 Characteristics 211 11 3 Pins and internal signals 212 11 4 Function overview 213 11 4 1 Foreground calibration function 213 11 4 2 ADC clock 214 11 4 3 ADC enable 214 11 4 4 Routine sequence 214 11 4 5 Operation modes 214 11 4 6 Conversion result threshold monitor fun...

Page 8: ...noise wave 237 12 3 7 DAC output calculate 238 12 3 8 DMA function 238 12 3 9 DAC concurrent conversion 238 12 4 Register definition 239 12 4 1 Control register DAC_CTL 239 12 4 2 Software trigger register DAC_SWT 241 12 4 3 DAC0 12 bit right aligned data holding register DAC0_R12DH 242 12 4 4 DAC0 12 bit left aligned data holding register DAC0_L12DH 242 12 4 5 DAC0 8 bit right aligned data holdin...

Page 9: ...C interrupt enable register RTC_INTEN 263 14 4 2 RTC control register RTC_CTL 263 14 4 3 RTC prescaler high register RTC_PSCH 264 14 4 4 RTC prescaler low register RTC_PSCL 265 14 4 5 RTC divider high register RTC_DIVH 265 14 4 6 RTC divider low register RTC_DIVL 265 14 4 7 RTC counter high register RTC_CNTH 266 14 4 8 RTC counter low register RTC_CNTL 266 14 4 9 RTC alarm high register RTC_ALRMH ...

Page 10: ... diagram 417 15 5 4 Function overview 417 15 5 5 Register definition 422 16 Universal synchronous asynchronous receiver transmitter USART 428 16 1 Overview 428 16 2 Characteristics 428 16 3 Function overview 429 16 3 1 USART frame format 430 16 3 2 Baud rate generation 431 16 3 3 USART transmitter 431 16 3 4 USART receiver 432 16 3 5 Use DMA for data buffer access 434 16 3 6 Hardware flow control ...

Page 11: ... 469 17 3 10 Packet error checking 469 17 3 11 SMBus support 470 17 3 12 Status errors and interrupts 471 17 4 Register definition 473 17 4 1 Control register 0 I2C_CTL0 473 17 4 2 Control register 1 I2C_CTL1 475 17 4 3 Slave address register 0 I2C_SADDR0 476 17 4 4 Slave address register 1 I2C_SADDR1 476 17 4 5 Transfer buffer register I2C_DATA 477 17 4 6 Transfer status register 0 I2C_STAT0 477 ...

Page 12: ...DATA 513 18 5 5 CRC polynomial register SPI_CRCPOLY 514 18 5 6 RX CRC register SPI_RCRC 514 18 5 7 TX CRC register SPI_TCRC 515 18 5 8 I2S control register SPI_I2SCTL 515 18 5 9 I2S clock prescaler register SPI_I2SPSC 517 19 Secure digital input output interface SDIO 519 19 1 Overview 519 19 2 Characteristics 519 19 3 SDIO bus topology 519 19 4 SDIO functional description 522 19 4 1 SDIO adapter 5...

Page 13: ...8 7 Data timeout register SDIO_DATATO 573 19 8 8 Data length register SDIO_DATALEN 573 19 8 9 Data control register SDIO_DATACTL 574 19 8 10 Data counter register SDIO_DATACNT 575 19 8 11 Status register SDIO_STAT 576 19 8 12 Interrupt clear register SDIO_INTC 577 19 8 13 Interrupt enable register SDIO_INTEN 578 19 8 14 FIFO counter register SDIO_FIFOCNT 580 19 8 15 FIFO data register SDIO_FIFO 58...

Page 14: ... x 0 2 649 21 4 11 Transmit mailbox data0 register CAN_TMDATA0x x 0 2 649 21 4 12 Transmit mailbox data1 register CAN_TMDATA1x x 0 2 650 21 4 13 Receive FIFO mailbox identifier register CAN_RFIFOMIx x 0 1 650 21 4 14 Receive FIFO mailbox property register CAN_RFIFOMPx x 0 1 651 21 4 15 Receive FIFO mailbox data0 register CAN_RFIFOMDATA0x x 0 1 652 21 4 16 Receive FIFO mailbox data1 register CAN_RF...

Page 15: ...4 14 MAC address 0 high register ENET_MAC_ADDR0H 722 22 4 15 MAC address 0 low register ENET_MAC_ADDR0L 722 22 4 16 MAC address 1 high register ENET_MAC_ADDR1H 723 22 4 17 MAC address 1 low register ENET_MAC_ADDR1L 724 22 4 18 MAC address 2 high register ENET_MAC_ADDR2H 724 22 4 19 MAC address 2 low register ENET_MAC_ADDR2L 725 22 4 20 MAC address 3 high register ENET_MAC_ADDR3H 725 22 4 21 MAC ad...

Page 16: ...register ENET_DMA_CTL 746 22 4 49 DMA interrupt enable register ENET_DMA_INTEN 749 22 4 50 DMA missed frame and buffer overflow counter register ENET_DMA_MFBOCNT 751 22 4 51 DMA current transmit descriptor address register ENET_DMA_CTDADDR 751 22 4 52 DMA current receive descriptor address register ENET_DMA_CRDADDR 752 22 4 53 DMA current transmit buffer address register ENET_DMA_CTBADDR 752 22 4 ...

Page 17: ... 24 2 Characteristics 773 24 3 Block diagram 774 24 4 Signal description 774 24 5 Function overview 774 24 5 1 USBFS clocks and working modes 774 24 5 2 USB host function 776 24 5 3 USB device function 778 24 5 4 OTG function overview 779 24 5 5 Data FIFO 780 24 5 6 Operation guide 783 24 6 Interrupts 787 24 7 Register definition 789 24 7 1 Global control and status registers 789 24 7 2 Host contr...

Page 18: ... HXTAL clock source 113 Figure 5 8 HXTAL clock source in bypass mode 114 Figure 6 1 Block diagram of EXTI 148 Figure 7 1 Basic structure of of a general pupose I O 154 Figure 7 2 Basic structure of Input configuration 155 Figure 7 3 Basic structure of Output configuration 156 Figure 7 4 Basic structure of Analog configuration 156 Figure 7 5 Basic structure of Alternate function configuration 157 F...

Page 19: ...f down counting mode 278 Figure 15 12 Channel input capture principle 279 Figure 15 13 channel output compare principle with complementary output x 0 1 2 280 Figure 15 14 channel output compare principle CH3_O 280 Figure 15 15 Output compare in three modes 282 Figure 15 16 Timing chart of EAPWM 283 Figure 15 17 Timing chart of CAPWM 283 Figure 15 18 Channel output complementary PWM with dead time ...

Page 20: ...ge TIMERx_CAR ongoing 370 Figure 15 54 Timing chart of center aligned counting mode 371 Figure 15 55 Channel input capture principle 372 Figure 15 56 channel output compare principle x 0 1 373 Figure 15 57 Output compare under three modes 374 Figure 15 58 EAPWM timechart 375 Figure 15 59 CAPWM timechart 376 Figure 15 60 Restart mode 377 Figure 15 61 Pause mode 378 Figure 15 62 Event mode 378 Figur...

Page 21: ... 5 SDA line arbitration 458 Figure 17 6 I2C communication flow with 7 bit address 458 Figure 17 7 I2C communication flow with 10 bit address Master Transmit 458 Figure 17 8 I2C communication flow with 10 bit address Master Receive 458 Figure 17 9 Programming model for slave transmitting mode 10 bit address mode 460 Figure 17 10 Programming model for slave receiving 10 bit address mode 462 Figure 1...

Page 22: ...iming diagram DTLEN 00 CHLEN 1 CKPL 1 499 Figure 18 28 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 0 CKPL 0 499 Figure 18 29 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 0 CKPL 1 499 Figure 18 30 PCM standard short frame synchronization mode timing diagram DTLEN 10 CHLEN 1 CKPL 0 499 Figure 18 31 PCM standard short frame synchronizatio...

Page 23: ...2 Read wait control by stopping SDIO_CLK 564 Figure 19 13 Read wait operation using SDIO_DAT 2 564 Figure 19 14 Function2 read cycle inserted during function1 multiple read cycle 565 Figure 19 15 Read Interrupt cycle timing 565 Figure 19 16 Write interrupt cycle timing 565 Figure 19 17 Multiple block 4 Bit read interrupt cycle timing 566 Figure 19 18 Multiple block 4 Bit write interrupt cycle timi...

Page 24: ... 21 11 The bit time 634 Figure 22 1 ENET module block diagram 658 Figure 22 2 MAC Tagged MAC frame format 659 Figure 22 3 Station management interface signals 661 Figure 22 4 Media independent interface signals 663 Figure 22 5 Reduced media independent interface signals 665 Figure 22 6 Wakeup frame filter register 679 Figure 22 7 System time update using the fine correction method 682 Figure 22 8 ...

Page 25: ...ne conversion AF remapping function 1 159 Table 7 5 TIMERx alternate function remapping 160 Table 7 6 TIMER4 alternate function remapping 1 161 Table 7 7 USART0 1 2 alternate function remapping 161 Table 7 8 I2C0 alternate function remapping 162 Table 7 9 SPI0 SPI2 I2S alternate function remapping 162 Table 7 10 CAN0 1 alternate function remapping 163 Table 7 11 ENET alternate function remapping 1...

Page 26: ...17 3 I2C error flags 471 Table 18 1 SPI signal description 484 Table 18 2 NSS function in slave mode 486 Table 18 3 NSS function in master mode 486 Table 18 4 SPI operation modes 487 Table 18 5 SPI interrupt requests 493 Table 18 6 I2S bitrate calculation formulas 502 Table 18 7 Audio sampling frequency calculation formulas 503 Table 18 8 Direction of I2S interface signals for each operation mode ...

Page 27: ...20 6 Mode 1 related registers configuration 591 Table 20 7 Mode A related registers configuration 593 Table 20 8 Mode 2 B related registers configuration 595 Table 20 9 Mode C related registers configuration 597 Table 20 10 Mode D related registers configuration 599 Table 20 11 Multiplex mode related registers configuration 601 Table 20 12 Timing configurations of synchronous multiplexed read mode...

Page 28: ...on status encoding 770 Table 23 5 Endpoint type encoding 770 Table 23 6 Endpoint kind meaning 770 Table 23 7 Transmission status encoding 770 Table 24 1 USBFS signal description 774 Table 24 2 USBFS global interrupt 787 Table 25 1 List of abbreviations used in register 848 Table 25 2 List of terms 848 Table 26 1 Revision history 850 ...

Page 29: ...cessor suitable for market products that require microcontrollers with high performance and low power consumption The Cortex M3 processor is based on the ARMv7 architecture and supports a powerful and scalable instruction set including general data processing I O control tasks and advanced data processing bit field manipulations Some system peripherals listed below are also provided by Cortex M3 I...

Page 30: ...D32F103xx microcontrollers with the flash memory density less than 256 Kbytes 1 2 System architecture A 32 bit multilayer bus is implemented in the GD32F10x devices which enables parallel access paths between multiple masters and slaves in the system The multilayer bus consists of an AHB interconnect matrix one AHB bus and two APB buses The interconnection relationship of the AHB interconnect matr...

Page 31: ...regions The System regions include the internal SRAM region and the Peripheral region DMA0 and DMA1 are the buses of DMA0 and DMA1 respectively ENET is the Ethernet There are also several slaves connected with the AHB interconnect matrix including FMC I FMC D SRAM EXMC AHB APB1 and APB2 FMC I is the instruction bus of the flash memory controller while FMC D is the data bus of the flash memory cont...

Page 32: ...IOA GPIOB USART1 2 SPI1 TIMER1 3 WWDGT CAN0 Slave Slave Slave Slave Slave Master Ibus Dbus Interrput request POR PDR PLL Fmax 108MHz LDO 1 2V IRC 8MHz LVD Powered By VDDA Master I2C0 I2C1 USBD FWDGT RTC Powered By VDDA GPIOC GPIOD GPIOE TIMER0 Slave EXMC ADC0 1 12 bit SAR ADC AHB Peripherals FMC CRC RCU ARM Cortex M3 Processor Fmax 108MHz SW JTAG System DCode ICode HXTAL 4 16MHz APB2 Fmax 108MHz A...

Page 33: ...2S1 2 TIMER1 3 WWDGT CAN0 Slave Slave Slave Slave Slave Master Ibus Dbus Interrput request POR PDR PLL Fmax 108MHz LDO 1 2V IRC 8MHz LVD Powered By VDDA Master I2C0 I2C1 USBD FWDGT RTC Powered By VDDA DAC GPIOC GPIOD GPIOE GPIOF Slave EXMC TIMER0 TIMER7 TIMER4 6 UART3 4 ADC0 2 12 bit SAR ADC AHB Peripherals FMC SDIO CRC RCU GPIOG ARM Cortex M3 Processor Fmax 108MHz SW JTAG System DCode ICode HXTAL...

Page 34: ...1 3 WWDGT CAN0 Slave Slave Slave Slave Slave Master Ibus Dbus Interrput request POR PDR PLL Fmax 108MHz LDO 1 2V IRC 8MHz LVD Powered By VDDA Master I2C0 I2C1 USBD FWDGT RTC Powered By VDDA DAC GPIOC GPIOD GPIOE GPIOF Slave EXMC TIMER0 TIMER7 TIMER8 10 TIMER4 6 UART3 4 TIMER 11 13 ADC0 2 12 bit SAR ADC AHB Peripherals FMC SDIO CRC RCU GPIOG ARM Cortex M3 Processor Fmax 108MHz SW JTAG System DCode ...

Page 35: ...DMA 12 chs Slave EXMC 12 bit SAR ADC Powered By VDDA ARM Cortex M3 Processor Fmax 108MHz SW JTAG System DCode ICode AHB Matrix APB2 Fmax 108MHz APB1 Fmax 54MHZ NOTE GD32F101xx series maximum system clock is 56MHz 1 3 Memory map The Arm Cortex M3 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load store data The instruction code and data are b...

Page 36: ... EXMC PC CARD 0x7000 0000 0x8FFF FFFF EXMC NAND 0x6000 0000 0x6FFF FFFF EXMC NOR PSRAM SRA M Peripheral AHB 0x5000 0000 0x5003 FFFF USBFS 0x4008 0000 0x4FFF FFFF Reserved 0x4004 0000 0x4007 FFFF Reserved 0x4002 BC00 0x4003 FFFF Reserved 0x4002 B000 0x4002 BBFF Reserved 0x4002 A000 0x4002 AFFF Reserved 0x4002 8000 0x4002 9FFF ENET 0x4002 6800 0x4002 7FFF Reserved 0x4002 6400 0x4002 67FF Reserved 0x...

Page 37: ... 0x4001 4FFF TIMER8 0x4001 4800 0x4001 4BFF Reserved 0x4001 4400 0x4001 47FF Reserved 0x4001 4000 0x4001 43FF Reserved 0x4001 3C00 0x4001 3FFF ADC2 0x4001 3800 0x4001 3BFF USART0 0x4001 3400 0x4001 37FF TIMER7 0x4001 3000 0x4001 33FF SPI0 0x4001 2C00 0x4001 2FFF TIMER0 0x4001 2800 0x4001 2BFF ADC1 0x4001 2400 0x4001 27FF ADC0 0x4001 2000 0x4001 23FF GPIOG 0x4001 1C00 0x4001 1FFF GPIOF 0x4001 1800 ...

Page 38: ...000 43FF Reserved 0x4000 3C00 0x4000 3FFF SPI2 I2S2 0x4000 3800 0x4000 3BFF SPI1 I2S1 0x4000 3400 0x4000 37FF Reserved 0x4000 3000 0x4000 33FF FWDGT 0x4000 2C00 0x4000 2FFF WWDGT 0x4000 2800 0x4000 2BFF RTC 0x4000 2400 0x4000 27FF Reserved 0x4000 2000 0x4000 23FF TIMER13 0x4000 1C00 0x4000 1FFF TIMER12 0x4000 1800 0x4000 1BFF TIMER11 0x4000 1400 0x4000 17FF TIMER6 0x4000 1000 0x4000 13FF TIMER5 0x...

Page 39: ... of read modify write operations the Cortex M3 processor provides a bit banding function to perform a single atomic bit operation The memory map includes two bit band regions These occupy the SRAM and Peripherals respectively These bit band regions map each word in an alias region of memory to a bit in a bit band region of memory A mapping formula shows how to reference each word in the alias regi...

Page 40: ...density devices GD32F10x_MD GD32F101xx and GD32F103xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes are called High density devices GD32F10x_HD GD32F101xx and GD32F103xx microcontrollers where the flash memory density is over 512 Kbytes are called Extra density devices GD32F10x_XD GD32F105xx and GD32F107xx microcontrollers are called connectivity line devices GD...

Page 41: ... FF00 please refer to Table 2 2 GD32F10x_CL and GD32F10x_HD GD32F10x_XD for other series addresses is aliased in the boot memory space which begins at the address 0x0000 0000 When the on chip SRAM whose memory space is beginning at 0x2000 0000 is selected as the boot source in the application initialization code you have to relocate the vector table in SRAM using the NVIC exception table and offse...

Page 42: ...0 FLASH_DENSITY 15 0 Flash memory density The value indicates the Flash memory density of the device in Kbytes Example 0x0020 indicates 32 Kbytes 1 5 2 Unique device ID 96 bits Base address 0x1FFF F7E8 The value is factory programmed and can never be altered by user 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNIQUE_ID 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNIQUE_ID 15 0 r Bits Fields ...

Page 43: ... 6 System configuration registers Base address 0x4002 103C Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CEE Reserved rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 CEE Code execution efficiency 0 Default code execution efficiency 1 Code execution efficiency enhancement 6 0 Reserved Must be k...

Page 44: ...ore than 512KB and GD32F10x_HD The flash page size is 1KB for GD32F10x_MD for other series the page size is 2KB for bank0 4KB for bank1 Word half word programming page erase and mass erase operation 16B option bytes block for user application requirements Flash security protection to prevent illegal code data access Page erase program protection to prevent unexpected operation 2 3 Function overvie...

Page 45: ...x0800 1000 0x0800 17FF 2KB Page 255 0x0807 F800 0x0807 FFFF 2KB Page 256 0x0808 0000 0x0808 0FFF 4KB Page 257 0x0808 1000 0x0808 1FFF 4KB Page 895 0x082F F000 0x082F FFFF 4KB Information Block GD32F10x_HD Boot loader area 0x1FFF F000 0x1FFF F7FF 2KB GD32F10x_XD 0x1FFF E000 0x1FFF F7FF 6KB GD32F10x_CL 0x1FFF B000 0x1FFF F7FF 18KB Option bytes Block Option bytes 0x1FFF F800 0x1FFF F80F 16B Note The ...

Page 46: ... and erase operations to bank1 The lock unlock mechanism of FMC_CTL1 register is similar to FMC_CTL0 register The unlock sequence should be written to FMC_KEY1 when unlocking FMC_CTL1 2 3 4 Page erase The FMC provides a page erase function which is used to initialize the contents of a main flash memory page to a high state Each page can be erased independently without affecting the contents of oth...

Page 47: ...t the PER bit Write FMC_ADDRx Is the LK bit is 0 Send the command to FMC by setting START bit Start Yes No Unlock the FMC_CTLx Is the BUSY bit is 0 Yes No Is the BUSY bit is 0 Yes No Finish For the GD32F10x_CL and GD32F10x_XD FMC_STAT0 reflects the operation status of bank0 and FMC_ STAT1 reflects the operation status of bank1 The page erase procedure applied to bank1 is similar to the procedure a...

Page 48: ... mass erase command to the FMC by setting the START bit in FMC_CTLx registers Wait until all the operations have been finished by checking the value of the BUSY bit in FMC_STATx registers Read and verify the flash memory if required using a DBUS access When the operation is executed successfully the ENDF in FMC_STATx registers is set and an interrupt will be triggered by FMC if the ENDIE bit in th...

Page 49: ...nlock the FMC_CTLx registers if necessary Check the BUSY bit in FMC_STATx registers to confirm that no flash memory operation is in progress BUSY equals to 0 Otherwise wait until the operation has finished Set the PG bit in FMC_CTLx registers Write a 32 bit word 16 bit half word to desired absolute address 0x08XX XXXX by DBUS Wait until all the operations have been finished by checking the value o...

Page 50: ...r WPERR bit in the FMC_STATx registers to detect which condition occurred in the interrupt handler The Figure 2 3 Process of word program operation displays the word programming operation flow Figure 2 3 Process of word program operation Set the PG bit Is the LK bit is 0 Perform word half word write by DBUS Start Yes No Unlock the FMC_CTLx Is the BUSY bit is 0 Yes No Is the BUSY bit is 0 Yes No Fi...

Page 51: ...are modified the MSB is generated by FMC automatically not the value of input data The following steps show the erase sequence Unlock the FMC_CTL0 register if necessary Check the BUSY bit in FMC_STAT0 register to confirm that no Flash memory operation is in progress BUSY equals to 0 Otherwise wait until the operation has finished Unlock the option bytes operation bits in FMC_CTL0 register if neces...

Page 52: ...eset instead of entering standby mode 1 no reset when entering standby mode 1 nRST_DPSLP 0 generate a reset instead of entering deep sleep mode 1 no reset when entering deep sleep mode 0 nWDG_HW 0 hardware free watchdog 1 software free watchdog 0x1fff f803 USER_N USER complement value 0x1fff f804 DATA 7 0 user defined data bit 7 to 0 0x1fff f805 DATA_N 7 0 DATA complement value bit 7 to 0 0x1fff f...

Page 53: ...2 3 11 Security protection The FMC provides a security protection function to prevent illegal code data access on the Flash memory This function is useful for protecting the software firmware from illegal users No protection when setting SPC byte and its complement value to 0x5AA5 no protection performed The main flash and option bytes block are accessible by all operations Under protection when s...

Page 54: ...lds Descriptions 31 3 Reserved Must be kept at reset value 2 0 WSCNT 2 0 Wait state counter These bits is set and reset by software The WSCNT valid when WSEN bit in FMC_WSEN is set 000 0 wait state added 001 1 wait state added 010 2 wait state added 011 111 reserved 2 4 2 Unlock key register 0 FMC_KEY0 Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 3...

Page 55: ...L0 option bytes operation unlock key These bits are only be written by software Write OBKEY 31 0 with keys to unlock option bytes command in FMC_CTL0 register 2 4 4 Status register 0 FMC_STAT0 Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ENDF WPERR ...

Page 56: ... Reset value 0x0000 0080 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ENDIE Reserved ERRIE OBWEN Reserved LK START OBER OBPG Reserved MER PER PG rw rw rw rs rs rw rw rw rw rw Bits Fields Descriptions 31 13 Reserved Must be kept at reset value 12 ENDIE End of operation interrupt enable bit Thi...

Page 57: ... by software 0 no effect 1 option bytes program command 3 Reserved Must be kept at reset value 2 MER Main flash mass erase for bank0 command bit This bit is set or cleared by software 0 no effect 1 main flash mass erase command for bank0 1 PER Main flash page erase for bank0 command bit This bit is set or clear by software 0 no effect 1 main flash page erase command for bank0 0 PG Main flash progr...

Page 58: ...DATA 15 6 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA 5 0 USER 7 0 SPC OBERR r r r r Bits Fields Descriptions 31 26 Reserved Must be kept at reset value 25 10 DATA 15 0 Store DATA of option bytes block after system reset 9 2 USER 7 0 Store USER of option bytes block after system reset 1 SPC Option bytes security protection code 0 no protection 1 protection 0 OBERR Option bytes read error bit This...

Page 59: ... 25 24 23 22 21 20 19 18 17 16 KEY 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY 15 0 w Bits Fields Descriptions 31 0 KEY 31 0 FMC_CTL1 unlock register These bits are only be written by software Write KEY 31 0 with keys to unlock FMC_CTL1 register 2 4 10 Status register 1 FMC_STAT1 Address offset 0x4C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 ...

Page 60: ...ash is busy bit When the operation is in progress this bit is set to 1 When the operation is end or an error is generated this bit is cleared to 0 2 4 11 Control register 1 FMC_CTL1 Address offset 0x50 Reset value 0x0000 0080 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ENDIE Reserved ERRIE R...

Page 61: ...software 0 no effect 1 main flash mass erase command for bank1 1 PER Main flash page erase for bank1 command bit This bit is set or clear by software 0 no effect 1 main flash page erase command for bank1 0 PG Main flash program for bank1 command bit This bit is set or clear by software 0 no effect 1 main flash program command for bank1 Note This register should be reset after the corresponding fla...

Page 62: ...ister This bit is set and reset by software This bit also protected by the FMC_KEYx register It is necessary to writing 0x45670123 and 0xCDEF89AB to the FMC_KEYx register 0 no wait state added when fetch flash 1 wait state added when fetch flash 2 4 14 Product ID register FMC_PID Address offset 0x100 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23...

Page 63: ...GD32F10x User Manual 63 programmed during the chip production ...

Page 64: ...ly overview The power of the VDD domain is supplied directly by VDD An embedded LDO in the VDD VDDA domain is used to supply the 1 2V domain power A power switch is implemented for the Backup domain It can be powered from the VBAT voltage when the main VDD supply is shut down 3 2 Characteristics Three power domains VBAK VDD VDDA and 1 2V power domains Three power saving modes Sleep Deep sleep and ...

Page 65: ...in can be connected to an optional standby voltage supplied by a battery or by another source The power switch is controlled by the power down reset circuit in the VDD VDDA domain If no external battery is used in the application it is recommended to connect VBAT pin externally to VDD pin with a 100nF external ceramic decoupling capacitor The Backup domain reset sources include the Backup domain p...

Page 66: ... output mode maximum load 30pF 3 3 2 VDD VDDA power domain VDD VDDA domain includes two parts VDD domain and VDDA domain VDD domain includes HXTAL high speed crystal oscillator LDO voltage regulator POR PDR power on down reset FWDGT free watchdog timer all pads except PC13 PC14 PC15 etc VDDA domain includes ADC DAC AD DA converter IRC8M Internal 8MHz RC oscillator IRC40K internal 40KHz RC oscillat...

Page 67: ..._CS indicates if VDD VDDA is higher or lower than the LVD threshold This event is internally connected to the EXTI line 16 and can generate an interrupt if it is enabled through the EXTI registers Figure 3 3 Waveform of the LVD threshold shows the relationship between the LVD threshold and the LVD output LVD interrupt signal depends on EXTI line 16 rising or falling edge configuration The followin...

Page 68: ...DDA domain etc Once the 1 2V is powered up the POR will generate a reset sequence on the 1 2V power domain If need to enter the expected power saving mode the associated control bits must be configured Then once a WFI Wait for Interrupt or WFE Wait for Event instruction is executed the device will enter an expected power saving mode which will be discussed in the following section 3 3 4 Power savi...

Page 69: ... the IRC8M is selected as the system clock Notice that an additional wakeup delay will be incurred if the LDO operates in low power mode Note In order to enter Deep sleep mode smoothly all EXTI line pending status in the EXTI_PD register and related peripheral flags must be reset refer toTable 6 3 EXTI source If not the program will skip the entry process of Deep sleep mode to continue to execute ...

Page 70: ...MOD 1 WURST 1 Entry WFI or WFE WFI or WFE WFI or WFE Wakeup Any interrupt for WFI Any event or interrupt when SEVONPEND is 1 for WFE Any interrupt from EXTI lines for WFI Any event or interrupt when SEVONPEND is 1 from EXTI for WFE 1 NRST pin 2 WKUP pin 3 FWDGT reset 4 RTC Wakeup Latency None IRC8M wakeup time LDO wakeup time added if LDO is in low power mode Power on sequence Note In standby mode...

Page 71: ...criptions 31 9 Reserved Must be kept at reset value 8 BKPWEN Backup Domain Write Enable 0 Disable write access to the registers in Backup domain 1 Enable write access to the registers in Backup domain After reset any write access to the registers in Backup domain is ignored This bit has to be set to enable write access to these registers 7 5 LVDT 2 0 Low Voltage Detector Threshold 000 2 2V 001 2 3...

Page 72: ... 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WUPEN Reserved LVDF STBF WUF rw r r r Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 WUPEN WKUP Pin Enable 0 Disable WKUP pin function 1 Enable WKUP pin function If WUPEN is set before entering the Standby mode a rising edge on the WKUP pin wakes up the system from the Standby mode As the WKUP pin is active hig...

Page 73: ...the Standby mode This bit is cleared only by a POR PDR or by setting the STBRST bit in the PMU_CTL register 0 WUF Wakeup Flag 0 No wakeup event has been received 1 Wakeup event occurred from the WKUP pin or the RTC alarm event This bit is cleared only by a POR PDR or by setting the WURST bit in the PMU_CTL register ...

Page 74: ... and writing access to the registers in Backup domain should be enabled by setting the BKPWEN bit in the PMU_CTL register 4 2 Characteristics 84 bytes Backup registers which can keep data under power saving mode If tamper event is detected Backup registers will be reset The active level of Tamper source PC13 can be configured RTC Clock Calibration register provides RTC alarm and second output sele...

Page 75: ...t used for tamper detection signal So the tamper detection configuration should be set before enable TAMPER pin When the tamper event is detected the corresponding TEF bit in the BKP_TPCS register will be set Tamper event can generate an interrupt if tamper interrupt is enabled Any tamper event will reset all Backup data registers Note When TPAL 0 1 if the TAMPER pin is already high low before it ...

Page 76: ...r power reset 4 4 2 RTC signal output control register BKP_OCTL Address offset 0x2C Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ROSEL ASOEN COEN RCCV 6 0 rw rw rw rw Bits Fields Descriptions 15 10 Reserved Must be kept at reset value 9 ROSEL RTC output selection 0 RTC alarm pulse is selected as the RTC output 1 ...

Page 77: ...ter BKP_TPCTL Address offset 0x30 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TPAL TPEN rw rw Bits Fields Descriptions 15 2 Reserved Must be kept at reset value 1 TPAL TAMPER pin active level 0 The TAMPER pin is active high 1 The TAMPER pin is active low 0 TPEN TAMPER detection enable 0 The TAMPER pin is free fo...

Page 78: ... No tamper event occurred 1 A tamper event occurred This bit is reset by writing 1 to the TER bit 7 3 Reserved Must be kept at reset value 2 TPIE Tamper interrupt enable 0 Disable the tamper interrupt 1 Enable the tamper interrupt This bit is reset only by a system reset and wake up from Standby mode 1 TIR Tamper interrupt reset 0 No effect 1 Reset the TIF bit This bit is always read as 0 0 TER Ta...

Page 79: ...ns 5 1 2 Function overview Power reset The power reset is generated by either an external reset as power on and power down reset POR PDR reset or by the internal reset generator when exiting Standby mode The power reset sets all registers to their reset values except the backup domain The power reset whose active signal is low it will be de asserted when the internal LDO voltage regulator is ready...

Page 80: ...reset is generated by setting the BKPRST bit in the backup domain control register or backup domain power on reset VDD or VBAT power on if both supplies have previously been powered off 5 2 Clock control unit CCTL 5 2 1 Overview The clock control unit provides a range of frequencies and clock functions These include an Internal 8M RC oscillator IRC8M a High Speed crystal oscillator HXTAL a Low Spe...

Page 81: ...or 2 PREDV0 NOTE GD32F101xx series maximum system clock is 56MHz The frequency of AHB APB2 and the APB1 domains can be configured by each prescaler The maximum frequency of the AHB APB2 and APB1 domains is 108 MHz 108 MHz 54 MHz The Cortex System Timer SysTick external clock is clocked with the AHB clock HCLK divided by 8 The SysTick can work either with this clock or with the AHB clock HCLK confi...

Page 82: ...IN OSCOUT C1 C2 Crystal The HXTAL crystal oscillator can be switched on or off using the HXTALEN bit in the control register RCU_CTL The HXTALSTB flag in control register RCU_CTL indicates if the high speed external crystal oscillator is stable When the HXTAL is powered up it will not be released for use until this HXTALSTB bit is set by the hardware This specific delay period is known as the osci...

Page 83: ...rer but its operating frequency is still less accurate than HXTAL The application requirements environment and cost will determine which oscillator type is selected If the HXTAL or PLL is the system clock source to minimize the time required for the system to recover from the Deep sleep Mode the hardware forces the IRC8M clock to be the system clock when the system initially wakes up Phase locked ...

Page 84: ...FWDGT counter Please refer to TIMER4CH3_IREMAP in AFIO_PCF0 register System clock CK_SYS selection After the system reset the default CK_SYS source will be IRC8M and can be switched to HXTAL or CK_PLL by changing the system clock switch bits SCS in the clock configuration register 0 RCU_CFG0 When the SCS value is changed the CK_SYS will continue to operate using the original clock source until the...

Page 85: ...ured in the properly alternate function I O AFIO mode to output the selected clock signal Table 5 1 Clock output 0 source select Clock Source 0 Selection bits Clock Source 0xx NO CLK 100 CK_SYS 101 CK_IRC8M 110 CK_HXTAL 111 CK_PLL 2 Voltage control The 1 2V domain voltage in Deep sleep mode can be controlled by DSLPVS 2 0 bit in the Deep sleep mode voltage register RCU_DSV Table 5 2 1 2V domain vo...

Page 86: ... stable 24 PLLEN PLL enable Set and reset by software This bit cannot be reset if the PLL clock is used as the system clock Reset by hardware when entering Deep sleep or Standby mode 0 PLL is switched off 1 PLL is switched on 23 20 Reserved Must be kept at reset value 19 CKMEN HXTAL clock monitor enable 0 Disable the High speed 4 16 MHz crystal oscillator HXTAL clock monitor 1 Enable the High spee...

Page 87: ... crystal oscillator enabled 15 8 IRC8MCALIB 7 0 Internal 8MHz RC oscillator calibration value register These bits are load automatically at power on 7 3 IRC8MADJ 4 0 Internal 8MHz RC oscillator clock trim adjust value These bits are set by software The trimming value is these bits IRC8MADJ added to the IRC8MCALIB 7 0 bits The trimming value should trim the IRC8M to 8 MHz 1 2 Reserved Must be kept ...

Page 88: ...o clock selected 100 System clock selected 101 Internel 8MHz RC Oscillator clock selected 110 External high speed oscillator clock selected 111 CK_PLL 2 clock selected 23 22 USBDPSC 1 0 USBD clock prescaler selection Set and reset by software to control the USBD clock prescaler value The USBD clock must be 48MHz These bits can t be reset if the USBD clock is enabled 00 CK_USBD CK_PLL 1 5 01 CK_USB...

Page 89: ... x 29 11101 CK_SYS CK_PLL x 30 11110 CK_SYS CK_PLL x 31 11111 CK_SYS CK_PLL x 32 17 PREDV0 PREDV0 division factor This bit is set and reset by software These bits can be written when PLL is disable 0 PREDV0 input source clock not divided 1 PREDV0 input source clock divided by 2 16 PLLSEL PLL clock source selection Set and reset by software to control the PLL clock source 0 IRC8M 2 clock selected a...

Page 90: ...elected 1000 CK_SYS 2 selected 1001 CK_SYS 4 selected 1010 CK_SYS 8 selected 1011 CK_SYS 16 selected 1100 CK_SYS 64 selected 1101 CK_SYS 128 selected 1110 CK_SYS 256 selected 1111 CK_SYS 512 selected 3 2 SCSS 1 0 System clock switch status Set and reset by hardware to indicate the clock source of system clock 00 Select CK_IRC8M as the CK_SYS source 01 Select CK_HXTAL as the CK_SYS source 10 Select...

Page 91: ... rw rw rw r r r r r r Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 CKMIC HXTAL clock stuck interrupt clear Write 1 by software to reset the CKMIF flag 0 Not reset CKMIF flag 1 Reset CKMIF flag 22 21 Reserved Must be kept at reset value 20 PLLSTBIC PLL stabilization interrupt clear Write 1 by software to reset the PLLSTBIF flag 0 Not reset PLLSTBIF flag 1 Reset PLLSTBIF fl...

Page 92: ...et by software to enable disable the IRC8M stabilization interrupt 0 Disable the IRC8M stabilization interrupt 1 Enable the IRC8M stabilization interrupt 9 LXTALSTBIE LXTAL stabilization interrupt enable LXTAL stabilization interrupt enable disable control 0 Disable the LXTAL stabilization interrupt 1 Enable the LXTAL stabilization interrupt 8 IRC40KSTBIE IRC40K stabilization interrupt enable IRC4...

Page 93: ...ock is stable and the LXTALSTBIE bit is set Reset when setting the LXTALSTBIC bit by software 0 No LXTAL stabilization interrupt generated 1 LXTAL stabilization interrupt generated 0 IRC40KSTBIF IRC40K stabilization interrupt flag Set by hardware when the Internal 40kHz RC oscillator clock is stable and the IRC40KSTBIE bit is set Reset when setting the IRC40KSTBIC bit by software 0 No IRC40K stabi...

Page 94: ...ER8 18 16 Reserved Must be kept at reset value 15 ADC2RST ADC2 reset This bit is set and reset by software 0 No reset 1 Reset the ADC2 14 USART0RST USART0 Reset This bit is set and reset by software 0 No reset 1 Reset the USART0 13 TIMER7RST Timer 7 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER7 12 SPI0RST SPI0 reset This bit is set and reset by software 0 No reset 1 Res...

Page 95: ...reset by software 0 No reset 1 Reset the GPIO port E 5 PDRST GPIO port D reset This bit is set and reset by software 0 No reset 1 Reset the GPIO port D 4 PCRST GPIO port C reset This bit is set and reset by software 0 No reset 1 Reset the GPIO port C 3 PBRST GPIO port B reset This bit is set and reset by software 0 No reset 1 Reset the GPIO port B 2 PARST GPIO port A reset This bit is set and rese...

Page 96: ...R12 RST TIMER11 RST TIMER6R ST TIMER5R ST TIMER4R ST TIMER3R ST TIMER2R ST TIMER1R ST rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 29 DACRST DAC reset This bit is set and reset by software 0 No reset 1 Reset DAC unit 28 PMURST Power control reset This bit is set and reset by software 0 No reset 1 Reset power control unit 27 BKPIRST Backup ...

Page 97: ...eset by software 0 No reset 1 Reset the UART3 18 USART2RST USART2 reset This bit is set and reset by software 0 No reset 1 Reset the USART2 17 USART1RST USART1 reset This bit is set and reset by software 0 No reset 1 Reset the USART1 16 Reserved Must be kept at reset value 15 SPI2RST SPI2 reset This bit is set and reset by software 0 No reset 1 Reset the SPI2 14 SPI1RST SPI1 reset This bit is set ...

Page 98: ...et 1 Reset the TIMER11 5 TIMER6RST TIMER6 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER6 4 TIMER5RST TIMER5 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER5 3 TIMER4RST TIMER4 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER4 2 TIMER3RST TIMER3 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER3 1 TIM...

Page 99: ...e 10 SDIOEN SDIO clock enable This bit is set and reset by software 0 Disabled SDIO clock 1 Enabled SDIO clock 9 Reserved Must be kept at reset value 8 EXMCEN EXMC clock enable This bit is set and reset by software 0 Disabled EXMC clock 1 Enabled EXMC clock 7 Reserved Must be kept at reset value 6 CRCEN CRC clock enable This bit is set and reset by software 0 Disabled CRC clock 1 Enabled CRC clock...

Page 100: ... 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TIMER10 EN TIMER9E N TIMER8E N Reserved rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC2EN USART0 EN TIMER7E N SPI0EN TIMER0E N ADC1EN ADC0EN PGEN PFEN PEEN PDEN PCEN PBEN PAEN Reserved AFEN rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields De...

Page 101: ...PI0EN SPI0 clock enable This bit is set and reset by software 0 Disabled SPI0 clock 1 Enabled SPI0 clock 11 TIMER0EN TIMER0 clock enable This bit is set and reset by software 0 Disabled TIMER0 clock 1 Enabled TIMER0 clock 10 ADC1EN ADC1 clock enable This bit is set and reset by software 0 Disabled ADC1 clock 1 Enabled ADC1 clock 9 ADC0EN ADC0 clock enable This bit is set and reset by software 0 Di...

Page 102: ...t and reset by software 0 Disabled GPIO port A clock 1 Enabled GPIO port A clock 1 Reserved Must be kept at reset value 0 AFEN Alternate function IO clock enable This bit is set and reset by software 0 Disabled Alternate Function IO clock 1 Enabled Alternate Function IO clock 5 3 8 APB1 enable register RCU_APB1EN Address offset 0x1C Reset value 0x0000 0000 This register can be accessed by byte 8 b...

Page 103: ... clock 1 Enabled backup interface clock 26 Reserved Must be kept at reset value 25 CAN0EN CAN0 clock enable This bit is set and reset by software 0 Disabled CAN0 clock 1 Enabled CAN0 clock 24 Reserved Must be kept at reset value 23 USBDEN USBD clock enable This bit is set and reset by software 0 Disabled USBD clock 1 Enabled USBD clock 22 I2C1EN I2C1 clock enable This bit is set and reset by softw...

Page 104: ...e This bit is set and reset by software 0 Disabled SPI2 clock 1 Enabled SPI2 clock 14 SPI1EN SPI1 clock enable This bit is set and reset by software 0 Disabled SPI1 clock 1 Enabled SPI1 clock 13 12 Reserved Must be kept at reset value 11 WWDGTEN WWDGT clock enable This bit is set and reset by software 0 Disabled WWDGT clock 1 Enabled WWDGT clock 10 9 Reserved Must be kept at reset value 8 TIMER13E...

Page 105: ...k 1 Enabled TIMER3 clock 1 TIMER2EN TIMER2 clock enable This bit is set and reset by software 0 Disabled TIMER2 clock 1 Enabled TIMER2 clock 0 TIMER1EN TIMER1 clock enable This bit is set and reset by software 0 Disabled TIMER1 clock 1 Enabled TIMER1 clock 5 3 9 Backup domain control register RCU_BDCTL Address offset 0x20 Reset value 0x0000 0000 reset by backup domain reset This register can be ac...

Page 106: ...oftware to control the RTC clock source Once the RTC clock source has been selected it cannot be changed anymore unless the backup domain is reset 00 No clock selected 01 CK_LXTAL selected as RTC source clock 10 CK_IRC40K selected as RTC source clock 11 CK_HXTAL 128 selected as RTC source clock 7 3 Reserved Must be kept at reset value 2 LXTALBPS LXTAL bypass mode enable Set and reset by software 0...

Page 107: ...TFC bit 0 No Low power management reset generated 1 Low power management reset generated 30 WWDGTRSTF Window watchdog timer reset flag Set by hardware when a window watchdog timer reset generated Reset by writing 1 to the RSTFC bit 0 No window watchdog reset generated 1 Window watchdog reset generated 29 FWDGTRSTF Free watchdog timer reset flag Set by hardware when a free watchdog timer reset gene...

Page 108: ...he IRC40K output clock is stable and ready for use 0 IRC40K is not stable 1 IRC40K is stable 0 IRC40KEN IRC40K enable Set and reset by software 0 Disable IRC40K 1 Enable IRC40K 5 3 11 Deep sleep mode voltage register RCU_DSV Address offset 0x34 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserv...

Page 109: ...GD32F10x User Manual 109 010 The core voltage is 1 0V in Deep sleep mode 011 The core voltage is 0 9V in Deep sleep mode 1xx Reserved ...

Page 110: ... PDR reset or by the internal reset generator when exiting standby mode The power reset sets all registers to their reset values except the backup domain The power reset whose active signal is low it will be de asserted when the internal LDO voltage regulator is ready to provide 1 2V power The RESET service routine vector is fixed at address 0x0000 0004 in the memory map System reset A system rese...

Page 111: ... or VBAT power on if both supplies have previously been powered off 5 5 Clock control unit CCTL 5 5 1 Overview The clock control unit provides a range of frequencies and clock functions These include a Internal 8M RC oscillator IRC8M a high speed crystal oscillator HXTAL a Low Speed Internal 40K RC oscillator IRC40K a low speed crystal oscillator LXTAL three Phase Lock Loop PLL a HXTAL clock monit...

Page 112: ... 1000 1001 1010 CK_PLL1 CK_PLL2 1011 CK_PLL2 1 2 3 15 16 PREDV1 8 14 16 20 PLL1 PLL1MF PLL2MF 8 14 16 20 PLL2 CK_PLL1 CK_PLL2 1 2 3 15 16 x2 I2S1 2SEL 0 1 CK_I2S 1 2 20 0 1 CK_MACTX 0 1 CK_MACRX Ethernet PHY EXT1 to CK_OUT CK_MACRMII PREDV0SEL MII_RMII_SEL CK_FMC to FMC NOTE GD32F101xx series maximum system clock is 54MHz The frequency of AHB APB2 and the APB1 domains can be configured by each pre...

Page 113: ...C oscillator IRC40K PLL clock source can be HXTAL or IRC8M HXTAL clock monitor 5 5 3 Function overview High speed crystal oscillator HXTAL The high speed external crystal oscillator HXTAL which has a frequency from 3 to 25 MHz produces a highly accurate clock source for use as the system clock A crystal with a specific frequency must be connected and located close to the two HXTAL pins The externa...

Page 114: ... register RCU_CTL is used to indicate if the internal 8M RC oscillator is stable The start up time of the IRC8M oscillator is shorter than the HXTAL crystal oscillator An interrupt can be generated if the related interrupt enable bit IRC8MSTBIE in the clock interrupt register RCU_INT is set when the IRC8M becomes stable The IRC8M clock can also be used as the system clock source or the PLL input c...

Page 115: ...ble bit LXTALSTBIE in the Interrupt Register RCU_INT is set when the LXTAL becomes stable Select external clock bypass mode by setting the LXTALBPS and LXTALEN bits in the backup domain control register RCU_BDCTL The CK_LXTAL is equal to the external clock which drives the OSC32IN pin Internal 40K RC oscillator IRC40K The internal RC oscillator has a frequency of about 40 kHz and is a low power cl...

Page 116: ...e HXTAL is selected as the clock source of PLL the HXTAL failure will force the PLL closed automatically If the HXTAL is selected as the clock source of RTC the HXTAL failure will reset the RTC clock selection Clock output capability The clock output capability is ranging from 0 09375 MHz to 108 MHz There are several clock signals can be selected via the CK_OUT0 clock source selection bits CKOUT0S...

Page 117: ...GD32F10x User Manual 117 010 1 0 011 0 9 ...

Page 118: ...ts Fields Descriptions 31 30 Reserved Must be kept at reset value 29 PLL2STB PLL2 clock stabilization flag Set by hardware to indicate if the PLL2 output clock is stable and ready for use 0 PLL2 is not stable 1 PLL2 is stable 28 PLL2EN PLL2 enable Set and reset by software Reset by hardware when entering Deep sleep or Standby mode 0 PLL2 is switched off 1 PLL2 is switched on 27 PLL1STB PLL1 clock ...

Page 119: ...ntrol bit IRC8MEN state 18 HXTALBPS High speed crystal oscillator HXTAL clock bypass mode enable The HXTALBPS bit can be written only if the HXTALEN is 0 0 Disable the HXTAL Bypass mode 1 Enable the HXTAL Bypass mode in which the HXTAL output clock is equal to the input clock 17 HXTALSTB High speed crystal oscillator HXTAL clock stabilization flag Set by hardware to indicate if the HXTAL oscillato...

Page 120: ... register 0 RCU_CFG0 Address offset 0x04 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PLLMF 4 ADCPSC 2 CKOUT0SEL 3 0 USBFSPSC 1 0 PLLMF 3 0 PREDV0 _LSB PLLSEL rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCPSC 1 0 APB2PSC 2 0 APB1PSC 2 0 AHBPSC 3 0 SCSS 1 0 SCS 1 0 rw rw ...

Page 121: ...ion factor Note The PLL output frequency must not exceed 108 MHz 00000 PLL source clock x 2 00001 PLL source clock x 3 00010 PLL source clock x 4 00011 PLL source clock x 5 00100 PLL source clock x 6 00101 PLL source clock x 7 00110 PLL source clock x 8 00111 PLL source clock x 9 01000 PLL source clock x 10 01001 PLL source clock x 11 01010 PLL source clock x 12 01011 PLL source clock x 13 01100 P...

Page 122: ... PLL 15 14 ADCPSC 1 0 ADC clock prescaler selection These bits and bit 28 of RCU_CFG0 are written by software to define the ADC prescaler factor Set and cleared by software 000 CK_APB2 2 selected 001 CK_APB2 4 selected 010 CK_APB2 6 selected 011 CK_APB2 8 selected 100 CK_APB2 2 selected 101 CK_APB2 12 selected 110 CK_APB2 8 selected 111 CK_APB2 16 selected 13 11 APB2PSC 2 0 APB2 prescaler selectio...

Page 123: ... whether the switching is complete or not The switch will be forced to IRC8M when leaving Deep sleep and Standby mode or HXTAL failure is detected by HXTAL clock monitor when HXTAL is selected directly or indirectly as the clock source of CK_SYS 00 Select CK_IRC8M as the CK_SYS source 01 Select CK_HXTAL as the CK_SYS source 10 Select CK_PLL as the CK_SYS source 11 Reserved 5 6 3 Clock interrupt re...

Page 124: ...eset PLLSTBIF flag 1 Reset PLLSTBIF flag 19 HXTALSTBIC HXTAL stabilization interrupt clear Write 1 by software to reset the HXTALSTBIF flag 0 Not reset HXTALSTBIF flag 1 Reset HXTALSTBIF flag 18 IRC8MSTBIC IRC8M stabilization interrupt clear Write 1 by software to reset the IRC8MSTBIF flag 0 Not reset IRC8MSTBIF flag 1 Reset IRC8MSTBIF flag 17 LXTALSTBIC LXTAL stabilization interrupt clear Write 1...

Page 125: ...IRC8M stabilization interrupt 0 Disable the IRC8M stabilization interrupt 1 Enable the IRC8M stabilization interrupt 9 LXTALSTBIE LXTAL stabilization interrupt enable LXTAL stabilization interrupt enable disable control 0 Disable the LXTAL stabilization interrupt 1 Enable the LXTAL stabilization interrupt 8 IRC40KSTBIE IRC40K stabilization interrupt enable IRC40K stabilization interrupt enable dis...

Page 126: ...r clock is stable and the IRC8MSTBIE bit is set Reset when setting the IRC8MSTBIC bit by software 0 No IRC8M stabilization interrupt generated 1 IRC8M stabilization interrupt generated 1 LXTALSTBIF LXTAL stabilization interrupt flag Set by hardware when the Low speed 32 768 Hz crystal oscillator clock is stable and the LXTALSTBIE bit is set Reset when setting the LXTALSTBIC bit by software 0 No LX...

Page 127: ...er 7 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER7 12 SPI0RST SPI0 reset This bit is set and reset by software 0 No reset 1 Reset the SPI0 11 TIMER0RST Timer 0 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER0 10 ADC1RST ADC1 reset This bit is set and reset by software 0 No reset 1 Reset the ADC1 9 ADC0RST ADC0 reset This bit is set and reset by ...

Page 128: ...are 0 No reset 1 Reset the GPIO port A 1 Reserved Must be kept at reset value 0 AFRST Alternate function I O reset This bit is set and reset by software 0 No reset 1 Reset Alternate Function I O 5 6 5 APB1 reset register RCU_APB1RST Address offset 0x10 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1...

Page 129: ...d reset by software 0 No reset 1 Reset backup interface 26 CAN1RST CAN1 reset This bit is set and reset by software 0 No reset 1 Reset the CAN1 25 CAN0RST CAN0 reset This bit is set and reset by software 0 No reset 1 Reset the CAN0 24 23 Reserved Must be kept at reset value 22 I2C1RST I2C1 reset This bit is set and reset by software 0 No reset 1 Reset the I2C1 21 I2C0RST I2C0 reset This bit is set...

Page 130: ...et by software 0 No reset 1 Reset the SPI2 14 SPI1RST SPI1 reset This bit is set and reset by software 0 No reset 1 Reset the SPI1 13 12 Reserved Must be kept at reset value 11 WWDGTRST WWDGT reset This bit is set and reset by software 0 No reset 1 Reset the WWDGT 10 6 Reserved Must be kept at reset value 5 TIMER6RST TIMER6 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER6 ...

Page 131: ...alf word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved ENETRX EN rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENETTX EN ENETEN Reserved USBFSE N Reserved EXMCEN Reserved CRCEN Reserved FMCSPE N Reserved SRAMSP EN DMA1EN DMA0EN rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 17 Reserved Must be kept at reset value 16 ENETRXEN Ethernet RX clock enable This bit...

Page 132: ...Enabled CRC clock 5 Reserved Must be kept at reset value 4 FMCSPEN FMC clock enable when sleep mode This bit is set and reset by software to enable disable FMC clock during Sleep mode 0 Disabled FMC clock during Sleep mode 1 Enabled FMC clock during Sleep mode 3 Reserved Must be kept at reset value 2 SRAMSPEN SRAM interface clock enable when sleep mode This bit is set and reset by software to enab...

Page 133: ... 31 15 Reserved Must be kept at reset value 14 USART0EN USART0 clock enable This bit is set and reset by software 0 Disabled USART0 clock 1 Enabled USART0 clock 13 TIMER7EN TIMER7 clock enable This bit is set and reset by software 0 Disabled TIMER7 clock 1 Enabled TIMER7 clock 12 SPI0EN SPI0 clock enable This bit is set and reset by software 0 Disabled SPI0 clock 1 Enabled SPI0 clock 11 TIMER0EN T...

Page 134: ...nable This bit is set and reset by software 0 Disabled GPIO port D clock 1 Enabled GPIO port D clock 4 PCEN GPIO port C clock enable This bit is set and reset by software 0 Disabled GPIO port C clock 1 Enabled GPIO port C clock 3 PBEN GPIO port B clock enable This bit is set and reset by software 0 Disabled GPIO port B clock 1 Enabled GPIO port B clock 2 PAEN GPIO port A clock enable This bit is s...

Page 135: ...ts Fields Descriptions 31 30 Reserved Must be kept at reset value 29 DACEN DAC clock enable This bit is set and reset by software 0 Disabled DAC clock 1 Enabled DAC clock 28 PMUEN PMU clock enable This bit is set and reset by software 0 Disabled PMU clock 1 Enabled PMU clock 27 BKPIEN Backup interface clock enable This bit is set and reset by software 0 Disabled backup interface clock 1 Enabled ba...

Page 136: ...s set and reset by software 0 Disabled USART2 clock 1 Enabled USART2 clock 17 USART1EN USART1 clock enable This bit is set and reset by software 0 Disabled USART1 clock 1 Enabled USART1 clock 16 Reserved Must be kept at reset value 15 SPI2EN SPI2 clock enable This bit is set and reset by software 0 Disabled SPI2 clock 1 Enabled SPI2 clock 14 SPI1EN SPI1 clock enable This bit is set and reset by so...

Page 137: ...d TIMER2 clock 1 Enabled TIMER2 clock 0 TIMER1EN TIMER1 clock enable This bit is set and reset by software 0 Disabled TIMER1 clock 1 Enabled TIMER1 clock 5 6 9 Backup domain control register RCU_BDCTL Address offset 0x20 Reset value 0x0000 0018 reset by backup domain reset This register can be accessed by byte 8 bit half word 16 bit and word 32 bit Note The LXTALEN LXTALBPS RTCSRC and RTCEN bits o...

Page 138: ...et 00 No clock selected 01 CK_LXTAL selected as RTC source clock 10 CK_IRC40K selected as RTC source clock 11 CK_HXTAL 128 selected as RTC source clock 7 3 Reserved Must be kept at reset value 2 LXTALBPS LXTAL bypass mode enable Set and reset by software 0 Disable the LXTAL Bypass mode 1 Enable the LXTAL Bypass mode 1 LXTALSTB Low speed crystal oscillator stabilization flag Set by hardware to indi...

Page 139: ...imer reset generated Reset by writing 1 to the RSTFC bit 0 No window watchdog reset generated 1 Window watchdog reset generated 29 FWDGTRSTF Free watchdog timer reset flag Set by hardware when a free watchdog timer reset generated Reset by writing 1 to the RSTFC bit 0 No free watchdog timer reset generated 1 free Watchdog timer reset generated 28 SWRSTF Software reset flag Set by hardware when a s...

Page 140: ... IRC40K enable Set and reset by software 0 Disable IRC40K 1 Enable IRC40K 5 6 11 AHB reset register RCU_AHBRST Address offset 0x28 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ENETRS T Reserved USBFSR ST Reserved rw rw Bits Fields Descripti...

Page 141: ...ction Set and reset by software to control the I2S2 clock source 0 System clock selected as I2S2 source clock 1 CK_PLL2 x 2 selected as I2S2 source clock 17 I2S1SEL I2S1 clock source selection Set and reset by software to control the I2S1 clock source 0 System clock selected as I2S1 source clock 1 CK_PLL2 x 2 selected as I2S1 source clock 16 PREDV0SEL PREDV0 input clock source selection Set and re...

Page 142: ...DV1 input source clock not divided 0001 PREDV1 input source clock divided by 2 0010 PREDV1 input source clock divided by 3 0011 PREDV1 input source clock divided by 4 0100 PREDV1 input source clock divided by 5 0101 PREDV1 input source clock divided by 6 0110 PREDV1 input source clock divided by 7 0111 PREDV1 input source clock divided by 8 1000 PREDV1 input source clock divided by 9 1001 PREDV1 i...

Page 143: ...V0 input source clock divided by 13 1101 PREDV0 input source clock divided by 14 1110 PREDV0 input source clock divided by 15 1111 PREDV0 input source clock divided by 16 5 6 13 Deep sleep mode voltage register RCU_DSV Address offset 0x34 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 ...

Page 144: ...ble peripheral interrupts 4 bits interrupt priority configuration 16 priority levels Efficient interrupt processing Support exception pre emption and tail chaining Wake up system from power saving mode Up to 20 independent edge detectors in EXTI Three trigger types rising falling and both edges Software interrupt or event trigger Trigger sources configurable 6 3 Function overview The Arm Cortex M3...

Page 145: ...Interrupt vector table Interrupt Number Vector Number Non connectivity devices Interrupt Description Connectivity devices Interrupt Description Vector Address IRQ 0 16 WWDGT interrupt WWDGT interrupt 0x0000_0040 IRQ 1 17 LVD from EXTI interrupt LVD from EXTI interrupt 0x0000_0044 IRQ 2 18 Tamper interrupt Tamper interrupt 0x0000_0048 IRQ 3 19 RTC global interrupt RTC global interrupt 0x0000_004C I...

Page 146: ...nterrupts 0x0000_009C IRQ 24 40 TIMER0 break interrupt and TIMER8 global interrupt TIMER0 break interrupt 0x0000_00A0 IRQ 25 41 TIMER0 update interrupt and TIMER9 global interrupt TIMER0 update interrupt 0x0000_00A4 IRQ 26 42 TIMER0 trigger and channel commutation interrupts and TIMER10 global interrupt TIMER0 trigger and channel commutation interrupts 0x0000_00A8 IRQ 27 43 TIMER0 channel capture ...

Page 147: ...erved 0x0000_00FC IRQ 48 64 EXMC global interrupt EXMC global interrupt 0x0000_0100 IRQ 49 65 SDIO global interrupt reserved 0x0000_0104 IRQ50 66 TIMER4 global interrupt TIMER4 global interrupt 0x0000_0108 IRQ51 67 SPI2 global interrupt SPI2 global interrupt 0x0000_010C IRQ52 68 UART3 global interrupt UART3 global interrupt 0x0000_0110 IRQ53 69 UART4 global interrupt UART4 global interrupt 0x0000_...

Page 148: ...e flash memory is less than 64KB IRQ30 IRQ33 IRQ34 IRQ36 and IRQ39 are not available 2 IRQ0 59 are available in HD and XD devices but the TIMER8 to TIMER13 global interrupts IRQ24 IRQ25 IRQ26 IRQ43 IRQ44 IRQ45 are available only in the XD devices 3 At non connectivity devices USB and CAN IRQ19 IRQ 20 function cannot be used at the same time 6 4 External interrupt and event EXTI block diagram Figur...

Page 149: ...ent SEV instructions The Wake up Interrupt Controller WIC enables the processor and NVIC to be put into a very low power sleep mode leaving the WIC to identify and prioritize interrupts and event EXTI can be used to wake up processor and the whole system when some expected event occurs such as a special GPIO pin toggling or RTC alarm Table 6 3 EXTI source EXTI Line Number Source 0 PA0 PB0 PC0 PD0 ...

Page 150: ...w rw Bits Fields Descriptions 31 20 Reserved Must be kept at reset value 19 0 INTENx Interrupt enable bit 0 Interrupt from Linex is disabled 1 Interrupt from Linex is enabled 6 6 2 Event enable register EXTI_EVEN Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved EVEN19 EVEN18 EVEN17 EVEN16 rw rw rw r...

Page 151: ...ENx Rising edge trigger enable 0 Rising edge of Linex is invalid 1 Rising edge of Linex is valid as an interrupt event request 6 6 4 Falling edge trigger enable register EXTI_FTEN Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FTEN19 FTEN18 FTEN17 FTEN16 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 152: ...t Event software trigger 0 Deactivate the EXTIx software interrupt event request 1 Activate the EXTIx software interrupt event request 6 6 6 Pending register EXTI_PD Address offset 0x14 Reset value undefined This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PD19 PD18 PD17 PD16 rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 ...

Page 153: ...ins can be configured by software as output push pull or open drain input peripheral alternate function or analog mode Each GPIO pin can be configured as pull up pull down or no pull up pull down All GPIOs are high current capable except for analog mode 7 2 Characteristics Input output direction control Schmitt trigger input function enable control Each pin weak pull up pull down function Output p...

Page 154: ...nate Function Input Input driver Output driver Registers Bit Operate Analog Input output Vdd Input Status Register I O pin ESD protect 7 3 1 GPIO pin configuration During or just after the reset period the alternative functions are all inactive and the GPIO ports are configured into the input floating mode that input disabled without Pull Up PU Pull Down PD resistors But the JTAG Serial Wired Debu...

Page 155: ...3 Alternate functions AF When the port is configured as AFIO set CTLy bits to 0b10 or 0b11 and set MDy bits to 0b01 0b10 or 0b11 which is in GPIOx_CTL0 GPIOx_CTL1 registers the port is used as peripheral alternate functions The detail alternate function assignments for each port are in the device datasheet 7 3 4 Input configuration When GPIO pin is configured as Input The schmitt trigger input is ...

Page 156: ...onfiguration Figure 7 3 Basic structure of Output configuration Read Vss Output Control Register Write Read Write Alternate Function Output Registers Bit Operate Output driver Vdd Input driver Input Status Register I O pin ESD protect 7 3 6 Analog configuration When GPIO pin is used as analog configuration The weak pull up and pull down resistors are disabled The output buffer is disabled The schm...

Page 157: ...iver Output driver Vdd I O pin ESD protect Alternate Function Output Alternate Function Input 7 3 8 IO pin function selection Each IO pin can implement many functions each function selected by GPIO registers GPIO Each IO pin can be used for GPIO input function by configuring MDy bits to 0b00 in GPIOx_CTL0 GPIOx_CTL1 registers And set output function by configuring MDy bits to 0b01 0b10 or 0b11 and...

Page 158: ... GPIO or the usage of peripheral functions each I O pin can be configured up to four different functions by setting the AFIO Port Configuration Register AFIO_PCF0 AFIO_PCF1 Suitable pinout locations can be selected using the peripheral IO remapping function Additionally various GPIO pins can be selected to be the EXTI interrupt line by setting the relevant EXTI Source Selection Register AFIO_EXTIS...

Page 159: ...ose I O 3 X Indicates that the corresponding pin can t be used as a general purpose I O 4 The SWJ Serial Wire JTAG supports JTAG or SWD access to the Cortex debug port The default state after reset is SWJ ON without trace This allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS JTCK pin 7 4 4 ADC AF remapping Refer to AFIO Port Configuration Register 0 AFIO_PCF0 Table 7...

Page 160: ...IMER0_CH1 PA9 PE11 TIMER0_CH2 PA10 PE13 TIMER0_CH3 PA11 PE14 TIMER0_BKIN PB12 2 PA6 PE15 TIMER0_CH0_ ON PB13 2 PA7 PE8 TIMER0_CH1_ ON PB14 2 PB0 PE10 TIMER0_CH2_ ON PB15 2 PB1 PE12 TIMER1_CH0 T IMER1_ETI 1 PA0 PA15 PA0 PA15 TIMER1_CH1 PA1 PB3 PA1 PB3 TIMER1_CH2 PA2 PB10 TIMER1_CH3 PA3 PB11 TIMER2_CH0 PA6 PA15 PC6 TIMER2_CH1 PA7 PB3 PC7 TIMER2_CH2 PB0 PB0 PC8 TIMER2_CH3 PB1 PB1 PC9 TIMER3_CH0 PB6 P...

Page 161: ...d 144 pin packages 7 TIMER8 9 10 12 13 refer to the AF remap and debug I O configuration register 1 AFIO_PCF1 Table 7 6 TIMER4 alternate function remapping 1 Alternate function TIMER4CH3_IREMAP 0 TIMER4CH3_IREMAP 1 TIMER4_CH3 TIMER4_CH3 is connected to PA3 IRC40K internal clock is connected to TIMER4_CH3 input for calibration purpose 1 Remap available only for High density and Extra density and Co...

Page 162: ... USART2_CTS PD12 USART2_RTS 1 Remap available only 100 pin and 144 pin packages 2 Remap available only for 64 pin 100 pin and 144 pin packages 3 Remap available only 100 pin and 144 pin packages 7 4 7 I2C0 AF remapping Refer to AFIO port configuration register 0 AFIO_PCF0 Table 7 8 I2C0 alternate function remapping Register I2C0_SCL I2C0_SDA I2C0_REMAP 0 PB6 PB7 I2C0_REMAP 1 PB8 PB9 7 4 8 SPI0 SPI...

Page 163: ...d on Port A Port B or Port D as shown in table below For port D remapping is not possible in devices delivered in 64 pin packages Table 7 10 CAN0 1 alternate function remapping Register 1 CAN0 CAN1 CAN0_REMAP 1 0 00 PA11 CAN0_RX PA12 CAN0_TX CAN0_REMAPI 1 0 10 PB8 CAN0_RX PB9 CAN0_TX CAN0_REMAP 1 0 11 2 PD0 CAN0_RX PD1 CAN0_TX CAN1_REMAP 0 PB12 CAN1_RX PB13 CAN1_TX CAN1_REMAP 1 PB5 CAN1_RX PB6 CAN...

Page 164: ... LXTAL has priority over the GPIOs function Note 1 But when the 1 8 V domain is powered off by entering standby mode or when the backup domain is supplied by VBAT VDD no more supplied the PC14 PC15 GPIO functionality is lost and will be set in analog mode 2 Refer to the note on IO usage restrictions in Section Backup domain Table 7 12 OSC32 pins configuration Alternate function LXTAL ON LXTAL OFF ...

Page 165: ...6 CTL7 1 0 MD7 1 0 CTL6 1 0 MD6 1 0 CTL5 1 0 MD5 1 0 CTL4 1 0 MD4 1 0 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTL3 1 0 MD3 1 0 CTL2 1 0 MD2 1 0 CTL1 1 0 MD1 1 0 CTL0 1 0 MD0 1 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 CTL7 1 0 Port 7 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 29 28 MD7 1 0 Port 7 mode bits These ...

Page 166: ...re refer to CTL0 1 0 description 13 12 MD3 1 0 Port 3 mode bits These bits are set and cleared by software refer to MD0 1 0 description 11 10 CTL2 1 0 Port 2 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 9 8 MD2 1 0 Port 2 mode bits These bits are set and cleared by software refer to MD0 1 0 description 7 6 CTL1 1 0 Port 1 configuration bits These bits...

Page 167: ...1 0 CTL13 1 0 MD13 1 0 CTL12 1 0 MD12 1 0 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTL11 1 0 MD11 1 0 CTL10 1 0 MD10 1 0 CTL9 1 0 MD9 1 0 CTL8 1 0 MD8 1 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 CTL15 1 0 Port 15 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 29 28 MD15 1 0 Port 15 mode bits These bits are set and cle...

Page 168: ...de bits These bits are set and cleared by software refer to MD0 1 0 description 11 10 CTL10 1 0 Port 10 configuration bits These bits are set and cleared by software refer to CTL0 1 0 description 9 8 MD10 1 0 Port 10 mode bits These bits are set and cleared by software refer to MD0 1 0 description 7 6 CTL9 1 0 Port 9 configuration bits These bits are set and cleared by software refer to CTL0 1 0 d...

Page 169: ... 15 0 ISTATy Port input status y 0 15 These bits are set and cleared by hardware 0 Input signal low 1 Input signal high 7 5 4 Port output control register GPIOx_OCTL x A G Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OCTL15 OCTL14 OCTL13 OCTL12 OCTL11 OCTL10...

Page 170: ...ftware 0 No action on the corresponding OCTLy bit 1 Clear the corresponding OCTLy bit to 0 15 0 BOPy Port Set bit y y 0 15 These bits are set and cleared by software 0 No action on the corresponding OCTLy bit 1 Set the corresponding OCTLy bit to 1 7 5 6 Port bit clear register GPIOx_BC x A G Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 ...

Page 171: ...iting Sequence And can always be read 0 GPIO_LOCK register is not locked and the port configuration is not locked 1 GPIO_LOCK register is locked until an MCU reset LOCK key configuration sequence Write 1 Write 0 Write 1 Read 0 Read 1 Note The value of LK 15 0 must hold during the LOCK Key Writing sequence 15 0 LKy Port Lock bit y y 0 15 These bits are set and cleared by software 0 The correspondin...

Page 172: ...tex EVENTOUT signal 0000 Select Pin 0 0001 Select Pin 1 0010 Select Pin 2 1111 Select Pin 15 7 5 9 AFIO port configuration register 0 AFIO_PCF0 Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit Memory map and bit definitions for Middle density High density and Extra density devices 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SPI2_RE MAP Reserv...

Page 173: ...routine conversion remapping This bit is set and reset by software 0 Connect the ADC1 external signal trigger routine conversion to EXTI11 1 Connect the ADC1 external signal trigger routine conversion to TIM7_TRGO 19 Reserved Must be kept at reset value 18 ADC0_ETRGRT_RE MAP ADC 0 external trigger routine conversion remapping This bit is set and reset by software 0 Connect the ADC0 external signal...

Page 174: ...PC6 TIMER2_CH1 PC7 TIMER2_CH2 PC8 TIMER2_CH3 PC9 9 8 TIMER1_REMAP 1 0 TIMER1 remapping These bits are set and reset by software 00 Disable the remapping function TIMER1_CH0 TIMER1_ETI PA0 TIMER1_CH1 PA1 TIMER1_CH2 PA2 TIMER1_CH3 PA3 01 Enable the remapping function partially TIMER1_CH0 TIMER1_ETI PA15 TIMER1_CH1 PB3 TIMER1_CH2 PA2 TIMER1_CH3 PA3 10 not used 11 Enable the remapping function fully T...

Page 175: ...SART1_TX PD5 USART1_RX PD6 USART1_CK PD7 2 USART0_REMAP USART0 remapping This bit is set and reset by software 0 Disable the remapping function USART0_TX PA9 USART0_RX PA10 1 Enable the remapping function USART0_TX PB6 USART0_RX PB7 1 I2C0_REMAP I2C0 remapping This bit is set and reset by software 0 Disable the remapping function I2C0_SCL PB6 I2C0_SDA PB7 1 Enable the remapping function I2C0_SCL P...

Page 176: ...PA15 SPI2_SCK I2S2_CK PB3 SPI2_MISO PB4 SPI2_MOSI I2S_SD PB5 1 Enable the remapping function fully SPI2_NSS I2S2_WS PA4 SPI2_SCK I2S2_CK PC10 SPI2_MISO PC11 SPI2_MOSI I2S_SD PC12 27 Reserved Must be kept at reset value 26 24 SWJ_CFG 2 0 Serial wire JTAG configuration Software can only write to this bit 000 JTAG DP Enabled and SW DP Enabled Reset State 001 JTAG DP Enabled and SW DP Enabled but with...

Page 177: ...0 Disable the remapping function TIMER2_CH0 PA6 TIMER2_CH1 PA7 TIMER2_CH2 PB0 TIMER2_CH3 PB1 01 Not used 10 Enable the remapping function partially TIMER2_CH0 PB4 TIMER2_CH1 PB5 TIMER2_CH2 PB0 TIMER2_CH3 PB1 11 Enable the remapping function fully TIMER2_CH0 PC6 TIMER2_CH1 PC7 TIMER2_CH2 PC8 TIMER2_CH3 PC9 9 8 TIMER1_REMAP 1 0 TIMER1 remapping 00 Disable the remapping function TIMER1_CH0 TIMER1_ETI...

Page 178: ... remapping 0 Disable the remapping function USART1_CTS PA0 USART1_RTS PA1 USART1_TX PA2 USART1_RX PA3 USART1_CK PA4 1 Enable the remapping function USART1_CTS PD3 USART1_RTS PD4 USART1_TX PD5 USART1_RX PD6 USART1_CK PD7 2 USART0_REMAP USART0 remapping 0 Disable the remapping function USART0_TX PA9 USART0_RX PA10 1 Enable the remapping function USART0_TX PB6 USART0_RX PB7 1 I2C0_REMAP I2C0 remappin...

Page 179: ...E3 pin 0101 PF3 pin 0110 PG3 pin Other configurations are reserved 11 8 EXTI2_SS 3 0 EXTI 2 sources selection 0000 PA2 pin 0001 PB2 pin 0010 PC2 pin 0011 PD2 pin 0100 PE2 pin 0101 PF2 pin 0110 PG2 pin Other configurations are reserved 7 4 EXTI1_SS 3 0 EXTI 1 sources selection 0000 PA1 pin 0001 PB1 pin 0010 PC1 pin 0011 PD1 pin 0100 PE1 pin 0101 PF1 pin 0110 PG1 pin Other configurations are reserve...

Page 180: ...0 EXTI6_SS 3 0 EXTI5_SS 3 0 EXTI4_SS 3 0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 EXTI7_SS 3 0 EXTI 7 sources selection 0000 PA7 pin 0001 PB7 pin 0010 PC7 pin 0011 PD7 pin 0100 PE7 pin 0101 PF7 pin 0110 PG7 pin Other configurations are reserved 11 8 EXTI6_SS 3 0 EXTI 6 sources selection 0000 PA6 pin 0001 PB6 pin 0010 PC6 pin 0011 PD6 pin 0100 PE6 pin 01...

Page 181: ...et 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI11_SS 3 0 EXTI10_SS 3 0 EXTI9_SS 3 0 EXTI8_SS 3 0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 EXTI11_SS 3 0 EXTI 11 sources selection 0000 PA11 pin 0001 PB11 pin 0010 PC11 pin 001...

Page 182: ... EXTI 8 sources selection 0000 PA8 pin 0001 PB8 pin 0010 PC8 pin 0011 PD8 pin 0100 PE8 pin 0101 PF8 pin 0110 PG8 pin Other configurations are reserved 7 5 13 EXTI sources selection register 3 AFIO_EXTISS3 Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI15_S...

Page 183: ... pin 0101 PF14 pin 0110 PG14 pin Other configurations are reserved 7 4 EXTI13_SS 3 0 EXTI 13 sources selection 0000 PA13 pin 0001 PB13 pin 0010 PC13 pin 0011 PD13 pin 0100 PE13 pin 0101 PF13 pin 0110 PG13 pin Other configurations are reserved 3 0 EXTI12_SS 3 0 EXTI 12 sources selection 0000 PA12 pin 0001 PB12 pin 0010 PC12 pin 0011 PD12 pin 0100 PE12 pin 0101 PF12 pin 0110 PG12 pin Other configura...

Page 184: ...ction PF9 8 TIMER12_REMAP TIMER12 remapping This bit is TIMER12_CH0 AF remapping control bit 0 Disable the remapping function PA6 1 Enable the remapping function PF8 7 TIMER10_REMAP TIMER10 remapping This bit is TIMER10_CH0 AF remapping control bit 0 Disable the remapping function PB9 1 Enable the remapping function PF7 6 TIMER9_REMAP TIMER9 remapping This bit is TIMER9_CH0 AF remapping control bi...

Page 185: ...period is 4 AHB clock cycles for 32 bit input data size from data entered to the calculation result available Free 8 bit register is unrelated to calculation and can be used for any other goals by any other peripheral devices Fixed polynomial 0x4C11DB7 X32 X26 X23 X22 X16 X12 X11 X10 X8 X7 X5 X4 X2 X 1 This 32 bit CRC polynomial is a common polynomial used in Ethernet Figure 8 1 Block diagram of C...

Page 186: ...gister has not been cleared by software setting the CRC_CTL register the new input raw data will be calculated based on the result of previous value of CRC_DATA During CRC calculation AHB will not be hanged because of the existence of the 32 bit input buffer This module supplies an 8 bit free register CRC_FDATA CRC_FDATA is unrelated to the CRC calculation any value you write in will be read out a...

Page 187: ...ware writes and reads This register is used to calculate new data and the register can be written the new data directly Written value cannot be read because the read value is the previous CRC calculation result 8 4 2 Free data register CRC_FDATA Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14...

Page 188: ... value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RST rs Bits Fields Descriptions 31 1 Reserved Must be kept at reset value 0 RST Set this bit can reset the CRC_DATA register to the value of 0xFFFFFFFF then automatically cleared itself to 0 by hardware This bit will take no effe...

Page 189: ...bus for some bus cycles Round robin scheduling is implemented in the bus matrix to ensure at least half of the system bus bandwidth for the CPU 9 2 Characteristics Programmable length of data to be transferred max to 65536 12 channels and each channel are configurable 7 for DMA0 and 5 for DMA1 AHB and APB peripherals FLASH SRAM can be accessed as source and destination Each channel is connected to...

Page 190: ...uests coming at the same time Channel management to control address data selection and data counting 9 4 Function overview 9 4 1 DMA operation Each DMA transfer consists of two operations including the loading of data from the source and the storage of the loaded data to the destination The source and destination addresses are computed by the DMA controller based on the programmed values in the DM...

Page 191: ...16 bits 16 bits 1 Read B1B0 15 0 0x0 2 Read B3B2 15 0 0x2 3 Read B5B4 15 0 0x4 4 Read B7B6 15 0 0x6 1 Write B1B0 15 0 0x0 2 Write B3B2 15 0 0x2 3 Write B5B4 15 0 0x4 4 Write B7B6 15 0 0x6 16 bits 8 bits 1 Read B1B0 15 0 0x0 2 Read B3B2 15 0 0x2 3 Read B5B4 15 0 0x4 4 Read B7B6 15 0 0x6 1 Write B0 7 0 0x0 2 Write B2 7 0 0x1 3 Write B4 7 0 0x2 4 Write B6 7 0 0x3 8 bits 32 bits 1 Read B0 7 0 0x0 2 Re...

Page 192: ...troller has initiated an AHB command to access the peripheral Figure 9 2 Handshake mechanism shows how the handshake mechanism works between the DMA controller and peripherals Figure 9 2 Handshake mechanism DMA Acknowledge Peripheral request Peripheral is ready to transmit or receive data and assert the request signal to DMA Peripheral request Peripheral request DMA acknowledge Wait the DMA bus id...

Page 193: ... the end of every DMA transfer DMA can always responds the peripheral request until the CHEN bit in the DMA_CHxCTL register is cleared 9 4 6 Memory to memory mode The memory to memory mode is enabled by setting the M2M bit in the DMA_CHxCTL register In this mode the DMA channel can also work without being triggered by a request from a peripheral The DMA channel starts transferring as soon as it is...

Page 194: ...TC register and a dedicated enable bit in the DMA_CHxCTL register The relationship is described in the following Table 9 2 Interrupt events Table 9 2 Interrupt events Interrupt event Flag bit Clear bit Enable bit DMA_INTF DMA_INTC DMA_CHxCTL Full transfer finish FTFIF FTFIFC FTFIE Half transfer finish HTFIF HTFIFC HTFIE Transfer error ERRIF ERRIFC ERRIE The DMA interrupt logic is shown in the Figu...

Page 195: ... 0 M2M Hardware priority high low SPI0_RX USART2_TX TIMER0_CH0 TIMER1_UP TIMER2_CH2 or or Channel 1 M2M SPI0_TX USART2_RX TIMER0_CH1 TIMER2_CH3 TIMER2_UP or or Channel 2 M2M SPI1 I2S1_RX USART0_TX I2C1_TX TIMER0_CH3 TIMER0_TG TIMER0_CMT TIMER3_CH1 or or Channel 3 M2M SPI1 I2S1_TX USART0_RX I2C1_RX TIMER0_UP TIMER1_CH0 TIMER3_CH2 or or Channel 4 M2M USART1_RX I2C0_TX TIMER0_CH2 TIMER2_CH0 TIMER2_TG...

Page 196: ...e 9 5 DMA1 request mapping SPI2 I2S2_RX TIMER4_CH3 TIMER4_TG TIMER7_CH2 TIMER7_UP or or Channel 0 M2M0 Hardware priority high low SPI2 I2S2_TX TIMER4_CH2 TIMER4_UP TIMER7_CH3 TIMER7_TG TIMER7_CMT or or Channel 1 M2M1 UART3_RX TIMER5_UP DAC_CH0 TIMER7_CH0 or or Channel 2 M2M2 SDIO TIMER4_CH1 TIMER6_UP DAC_CH1 or or Channel 3 M2M3 ADC2 UART3_TX TIMER4_CH0 TIMER7_CH1 or or Channel 4 M2M4 Table 9 4 DM...

Page 197: ...0x User Manual 197 Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 TIMER7_UP TIMER7_TG TIMER7_CMT ADC2 ADC2 DAC DAC_CH0 DAC_CH1 SPI I2S SPI2 I2S2_RX SPI2 I2S2_TX USART UART3_RX UART3_TX SDIO SDIO ...

Page 198: ... Must be kept at reset value 27 23 19 15 11 7 3 ERRIFx Error flag of channel x x 0 6 Hardware set and software cleared by configuring DMA_INTC register 0 Transfer error has not occurred on channel x 1 Transfer error has occurred on channel x 26 22 18 14 10 6 2 HTFIFx Half transfer finish flag of channel x x 0 6 Hardware set and software cleared by configuring DMA_INTC register 0 Half number of tra...

Page 199: ...e 27 23 19 15 11 7 3 ERRIFCx Clear bit for error flag of channel x x 0 6 0 No effect 1 Clear error flag 26 22 18 14 10 6 2 HTFIFCx Clear bit for half transfer finish flag of channel x x 0 6 0 No effect 1 Clear half transfer finish flag 25 21 17 13 9 5 1 FTFIFCx Clear bit for full transfer finish flag of channel x x 0 6 0 No effect 1 Clear full transfer finish flag 24 20 16 12 8 4 0 GIFCx Clear glo...

Page 200: ...tra high These bits can not be written when CHEN is 1 11 10 MWIDTH 1 0 Transfer data size of memory Software set and cleared 00 8 bit 01 16 bit 10 32 bit 11 Reserved These bits can not be written when CHEN is 1 9 8 PWIDTH 1 0 Transfer data size of peripheral Software set and cleared 00 8 bit 01 16 bit 10 32 bit 11 Reserved These bits can not be written when CHEN is 1 7 MNAGA Next address generatio...

Page 201: ...nterrupt 2 HTFIE Enable bit for channel half transfer finish interrupt Software set and cleared 0 Disable channel half transfer finish interrupt 1 Enable channel half transfer finish interrupt 1 FTFIE Enable bit for channel full transfer finish interrupt Software set and cleared 0 Disable channel full transfer finish interrupt 1 Enable channel full transfer finish interrupt 0 CHEN Channel enable S...

Page 202: ...nel x peripheral base address register DMA_CHxPADDR x 0 6 where x is a channel number Address offset 0x10 0x14 x Reset value 0x0000 0000 Note Do not configure this register when channel is enabled This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PADDR 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PADDR 15 0 rw Bits Fields Descriptions 31 0 PADDR 31 0...

Page 203: ... 12 11 10 9 8 7 6 5 4 3 2 1 0 MADDR 15 0 rw Bits Fields Descriptions 31 0 MADDR 31 0 Memory base address These bits can not be written when CHEN in the DMA_CHxCTL register is 1 When MWIDTH in the DMA_CHxCTL register is 01 16 bit the LSB of these bits is ignored Access is automatically aligned to a half word address When MWIDTH in the DMA_CHxCTL register is 10 32 bit the two LSBs of these bits are ...

Page 204: ...accessed by a debug tool via Serial Wire SW Debug Port or JTAG interface JTAG Debug Port 10 2 1 Switch JTAG or SW interface By default the JTAG interface is active The sequence for switching from JTAG to SWD is Send 50 or more TCK cycles with TMS 1 Send the 16 bit sequence on TMS 1110011110011110 0xE79E LSB first Send 50 or more TCK cycles with TMS 1 The sequence for switching from SWD to JTAG is ...

Page 205: ... bit BYPASS instruction 5 b 11111 for BSD JTAG and then shift normal 4 bit instruction for Cortext M3 JTAG Because of the data shift under BSD JTAG BYPASS mode adding 1 extra bit to the data chain is needed The BSD JTAG IDCODE is 0x790007A3 10 2 4 Debug reset The JTAG DP and SW DP register are in the power on reset domain The System reset initializes the majority of the Cortex M3 excluding NVIC an...

Page 206: ...n debug in Deep sleep mode When SLP_HOLD bit in DBG control register DBG_CTL is set and entering the sleep mode the clock of AHB bus for CPU is not closed and the debugger can debug in sleep mode 10 3 2 Debug support for TIMER I2C WWDGT FWDGT and CAN When the core halted and the corresponding bit in DBG control register DBG_CTL is set the following behaved For TIMER the timer counters stopped and ...

Page 207: ...r has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TIMER10 _HOLD TIMER9_ HOLD TIMER8_ HOLD TIMER13 _HOLD TIMER12 _HOLD TIMER11 _HOLD Reserved CAN1_H OLD TIMER6_ HOLD TIMER5_ HOLD TIMER4_ HOLD TIMER7_ HOLD I2C1_HO LD rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2C0_HO LD CAN0_H OLD TIMER3_ HOLD TIMER2_ HOLD TIMER1_ HOLD TIMER0_...

Page 208: ...alted 25 TIMER11_HOLD TIMER11 hold bit This bit is set and reset by software 0 no effect 1 hold the TIMER11 counter for debug when core halted 24 22 Reserved Must be kept at reset value 21 CAN1_HOLD CAN1 hold bit This bit is set and reset by software 0 no effect 1 the receive register of CAN1 stops receiving data when core halted 20 TIMER6_HOLD TIMER6 hold bit This bit is set and reset by software...

Page 209: ...TIMER3_HOLD TIMER3 hold bit This bit is set and reset by software 0 no effect 1 hold the TIMER3 counter for debug when core halted 12 TIMER2_HOLD TIMER2 hold bit This bit is set and reset by software 0 no effect 1 hold the TIMER2 counter for debug when core halted 11 TIMER1_HOLD TIMER1 hold bit This bit is set and reset by software 0 no effect 1 hold the TIMER1 counter for debug when core halted 1...

Page 210: ...is set and reset by software 0 Trace pin allocation disable 1 Trace pin allocation enable 4 3 Reserved Must be kept at reset value 2 STB_HOLD Standby mode hold bit This bit is set and reset by software 0 no effect 1 At the standby mode the clock of AHB bus and system clock are provided by CK_IRC8M a system reset generated when exit standby mode 1 DSLP_HOLD Deep sleep mode hold bit This bit is set ...

Page 211: ...e Data storage mode the most significant bit MSB and the least significant bit LSB DMA support Analog input channels 16 external analog inputs 1 channel for internal temperature sensor VSENSE 1 channel for internal reference voltage VREFINT Start of conversion can be initiated By software By hardware triggers Operation modes Converts a single channel or scans a sequence of channels Single operatio...

Page 212: ...n VSENSE Internal temperature sensor output voltage VREFINT Internal voltage reference output voltage Table 11 2 ADC input pins definition Name Description VDDA Analog power supply equal to VDD and 2 6 V VDDA 3 6 V VSSA Ground for analog power supply equal to VSS VREF The positive reference voltage for the ADC 2 6 V VREF VDDA VREF The negative reference voltage for the ADC VREF VSSA ADCx_IN 15 0 U...

Page 213: ...is internally applied to the ADC until the next ADC power off The application must not use the ADC during calibration and must wait until it is completed Calibration should be performed before starting A D conversion The calibration is initiated by setting bit CLB 1 CLB bit stays at 1 during all the calibration sequence It is then cleared by hardware as soon as the calibration is completed When th...

Page 214: ...nce The channel management circuit can organize the sampling conversion channels into a sequence routine sequence The routine sequence supports up to 16 channels and each channel is called routine channel The RL 3 0 bits in the ADC_RSQ0 register specify the total conversion sequence length The ADC_RSQ0 ADC_RSQ2 registers specify the selected channels of the routine sequence Note Although the ADC s...

Page 215: ...rsion on the channel specified in the RSQ0 4 0 When the ADCON has been set high the ADC samples and converts specified channel once the corresponding software trigger or external trigger is active The conversion data will be stored in the ADC_RDATA register Figure 11 3 Continuous operation mode CH2 CH2 CH2 CH2 CH2 CH2 EOC Routine trigger Sample Convert CH2 Software procedure for continuous operati...

Page 216: ...register must be set when the routine sequence works in scan mode After conversion of a routine sequence the conversion can be restarted automatically if the CTN bit in the ADC_CTL1 register is set Figure 11 4 Scan operation mode continuous disable CH2 CH1 CH5 CH7 CH11 CH16 CH2 CH1 EOC One circle of routine sequence RL 7 Routine trigger CH12 CH17 Software procedure for scan operation mode on a rou...

Page 217: ... ADC_SAMPTx registers 4 Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need 5 Prepare the DMA module to transfer data from the ADC_RDATA refer to the spec of the DMA module 6 Set the SWRCST bit or generate an external trigger for the routine sequence 7 Repeat step6 if in need 8 Wait the EOC flag to be set 9 Clear the EOC flag by writing 0 to it 11 4 6 Conversion result threshold mon...

Page 218: ...mple time is 1 5 cycles the total conversion time is 1 5 12 5 CK_ADC cycles that means 1us 11 4 9 External trigger configuration The conversion of routine sequence can be triggered by rising edge of external trigger inputs The external trigger source of routine sequence is controlled by the ETSRC 2 0 bits in the ADC_CTL1 register Table 11 3 External trigger source for ADC0 and ADC1 ETSRC 2 0 Trigg...

Page 219: ...ature sensor changes linearly with temperature Because there is an offset which is up to 45 C and varies from chip to chip due to the chip production process variation the internal temperature sensor is more appropriate to detect temperature variations instead of absolute temperature When it is used to detect accurate temperature an external temperature sensor part should be used to calibrate the ...

Page 220: ...t be enabled for ADC0 and ADC1 The following modes can be configured in Table 11 5 ADC sync mode table Table 11 5 ADC sync mode table SYNCM 2 0 mode 0000 Free mode 0110 Routine parallel mode 0111 Routine follow up fast mode 1000 Routine follow up slow mode In ADC sync mode the DMA bit must be set even if it is not used the converted data of ADC1 routine channel can be read from the ADC0 data regis...

Page 221: ...5 0 bits field to SRAM Note 1 If two ADCs use the same sampling channel it should be ensured that the channel is not used at the same time 2 Two channels sampled by two ADCs at the same time should be configured with the same sampling time Figure 11 9 Routine parallel mode on 10 channels CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 ADC0 ADC1 Routine trigger CH8 CH12 Sample Convert CH9 CH13 CH0 CH4 CH1 CH5 EOC ...

Page 222: ...gister When the trigger occurs ADC1 runs immediately ADC0 runs after 14 ADC clock cycles after the second 14 ADC clock cycles the ADC1 runs again Continuous mode can t be used in this mode because it continuously converts the routine channel The behavior of follow up slow mode shows in the Figure 11 11 Routine follow up slow mode After an EOC interrupt is generated by ADC0 if EOCIE bit is set we c...

Page 223: ...GD32F10x User Manual 223 11 6 ADC interrupts The interrupt can be produced on one of the events End of conversion for routine sequence The analog watchdog event ...

Page 224: ...ce conversion 0 Conversion is not started 1 Conversion is started Set by hardware when routine sequence conversion starts Cleared by software writing 0 to it 3 2 Reserved Must be kept at reset value 1 EOC End flag of routine sequence conversion 0 No end of routine sequence conversion 1 End ofroutine sequence conversion Set by hardware at the end of a routine sequence conversion Cleared by software...

Page 225: ... reset value 19 16 SYNCM 3 0 Sync mode selection These bits use to select the operating mode 0000 Free mode 0001 0101 Reserved 0110 Routine parallel mode 0111 Routine follow up fast mode 1000 Routine follow up slow mode 1001 1111 Reserved Note 1 These bits are only used in ADC0 2 Users must disable sync mode before any configuration change 15 13 DISNUM 2 0 Number of conversions in discontinuous mo...

Page 226: ...C channel2 00011 ADC channel 3 00100 ADC channel 4 00101 ADC channel 5 00110 ADC channel 6 00111 ADC channel 7 01000 ADC channel 8 01001 ADC channel 9 01010 ADC channel 10 01011 ADC channel 11 01100 ADC channel 12 01101 ADC channel 13 01110 ADC channel 14 01111 ADC channel15 10000 ADC channel16 10001 ADC channel17 Other values are reserved Note ADC0 analog inputs Channel16 and Channel17 are intern...

Page 227: ...conversion of routine sequence Set 1 on this bit starts a conversion of a routine sequence if ETSRC is 111 It is set by software and cleared by software or by hardware immediately after the conversion starts 21 Reserved Must be kept at reset value 20 ETERC External trigger enable for routine sequence 0 External trigger for routine sequence disable 1 External trigger for routine sequence enable 19 ...

Page 228: ...ibration done 1 Calibration start 1 CTN Continuous mode 0 Continuous operation mode disable 1 Continuous operation mode enable 0 ADCON ADC ON The ADC will be wake up when this bit is changed from low to high and take a stabilization time When this bit is high and 1 is written to it with other bits of this register unchanged the conversion will start 0 ADC disable and power down 1 ADC enable 11 7 4...

Page 229: ...me is 7 5 cycles 010 channel sampling time is 13 5 cycles 011 channel sampling time is 28 5 cycles 100 channel sampling time is 41 5 cycles 101 channel sampling time is 55 5 cycles 110 channel sampling time is 71 5 cycles 111 channel sampling time is 239 5 cycles 11 7 5 Sample time register 1 ADC_SAMPT1 Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 ...

Page 230: ...ycles 010 channel sampling time is 13 5 cycles 011 channel sampling time is 28 5 cycles 100 channel sampling time is 41 5 cycles 101 channel sampling time is 55 5 cycles 110 channel sampling time is 71 5 cycles 111 channel sampling time is 239 5 cycles 11 7 6 Watchdog high threshold register ADC_WDHT Address offset 0x24 Reset value 0x0000 0FFF This register has to be accessed by word 32 bit 31 30 ...

Page 231: ... 11 7 8 Routine sequence register 0 ADC_RSQ0 Address offset 0x2C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RL 3 0 RSQ15 4 1 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSQ15 0 RSQ14 4 0 RSQ13 4 0 RSQ12 4 0 rw rw rw rw Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 20 RL 3 0 Routine sequen...

Page 232: ...ion 24 20 RSQ10 4 0 refer to RSQ0 4 0 description 19 15 RSQ9 4 0 refer to RSQ0 4 0 description 14 10 RSQ8 4 0 refer to RSQ0 4 0 description 9 5 RSQ7 4 0 refer to RSQ0 4 0 description 4 0 RSQ6 4 0 refer to RSQ0 4 0 description 11 7 10 Routine sequence register 2 ADC_RSQ2 Address offset 0x34 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 233: ...sequence 11 7 11 Routine data register ADC_RDATA Address offset 0x4C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADC1RDTR 15 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDATA 15 0 r Bits Fields Descriptions 31 16 ADC1RDTR 15 0 ADC1 routine channel data In sync mode these bits contain the routine data of ADC1 These bits are o...

Page 234: ...t voltage can be optionally buffered for higher drive capability The two DACs can work independently or concurrently 12 2 Characteristics The main features of DAC are as follows 8 bit or 12 bit resolution Right or left data alignment DMA support Conversion update synchronously Conversion triggered by external triggers Configurable internal buffer Extern voltage reference VREF Noise wave LFSR noise...

Page 235: ...te The TIMER7_TRGO trigger is replaced by TIMER2_TRGO In connectivity line devices Table 12 1 DAC pins Name Description Signal type VDDA Analog power supply Power VSSA Ground for analog power supply Power VREF reference voltage Analog input DACx_OUT DACx analog output Analog output The GPIO pins PA4 for DAC0 PA5 for DAC1 should be configured to analog mode before enable the DAC module 12 3 Functio...

Page 236: ...gers of DAC Table 12 2 External triggers of DAC DTSELx 2 0 Trigger Source Trigger Type 3b 000 TIMER5_TRGO Hardware trigger 3b 001 TIMER2_TRGO in connectivity line devices TIMER7_TRGO in other type devices 3b 010 TIMER6_TRGO 3b 011 TIMER4_TRGO 3b 100 TIMER1_TRGO 3b 101 TIMER3_TRGO 3b 110 EXTI9 3b 111 SWTRIG Software trigger The TIMERx_TRGO signals are generated from the timers while the software tr...

Page 237: ...t Register LFSR in the DAC control logic it controls the LFSR noise signal which is added to the DACx_DH value When the configured DAC noise wave bit width is less than 12 the noise signal equals to the LSB DWBWx bits of the LFSR register while the MSB bits are masked Figure 12 2 DAC LFSR algorithm 9 7 8 6 5 4 3 2 1 11 10 0 X6 X0 X4 X XOR X12 NOR 12 Triangle noise mode in this mode a triangle sign...

Page 238: ... to maximize the utilization of the bus bandwidth we can make the two DACs work at the same time using concurrent mode In this mode the data transfer DACx_DH to DACx_DO of two DACs is performing at the same time There are three concurrent registers that can be used to load the DACx_DH value DACC_R8DH DACC_R12DH and DACC_L12DH One of the three registers needs to be configured for driving two DACs a...

Page 239: ...BW1 3 0 DAC1 noise wave bit width These bits specify bit width of the noise wave signal of DAC1 These bits indicate that unmask LFSR bit n 1 0 in LFSR noise mode or the amplitude of the triangle is 2 n 1 1 in triangle noise mode where n is the bit width of wave 0000 The bit width of the wave signal is 1 0001 The bit width of the wave signal is 2 0010 The bit width of the wave signal is 3 0011 The ...

Page 240: ...DAC1 output buffer turn on to reduce the output impedance and improve the driving capability 1 DAC1 output buffer turn off 16 DEN1 DAC1 enable 0 DAC1 disabled 1 DAC1 enabled 15 13 Reserved Must be kept at reset value 12 DDMAEN0 DAC0 DMA enable 0 DAC0 DMA mode disabled 1 DAC0 DMA mode enabled 11 8 DWBW0 3 0 DAC0 noise wave bit width These bits specify bit width of the noise wave signal of DAC0 Thes...

Page 241: ...ection These bits select the external trigger of DAC0 when DTEN0 1 000 Timer 5 TRGO 001 Timer 2 TRGO connectivity line devices Timer 7 TRGO other type devices 010 Timer 6 TRGO 011 Timer 4 TRGO 100 Timer 1 TRGO 101 Timer 3 TRGO 110 EXTI line 9 111 Software trigger 2 DTEN0 DAC0 trigger enable 0 DAC0 trigger disabled 1 DAC0 trigger enabled 1 DBOFF0 DAC0 output buffer turn off 0 DAC0 output buffer tur...

Page 242: ...register DAC0_R12DH Address offset 0x08 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DAC0_DH 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 DAC0_DH 11 0 DAC0 12 bit right aligned data These bits specify the data that is to be converted...

Page 243: ...ter has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DAC0_DH 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 DAC0_DH 7 0 DAC0 8 bit right aligned data These bits specify the MSB 8 bits of the data that is to be converted by DAC0 12 4 6 DAC1 12 bit right aligned data holding regist...

Page 244: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DAC1_DH 11 0 Reserved rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 4 DAC1_DH 11 0 DAC1 12 bit left aligned data These bits specify the data that is to be converted by DAC1 3 0 Reserved Must be kept at reset value 12 4 8 DAC1 8 bit right aligned data holding register DAC1_R8DH Address offset 0x1C Reset value 0x0000 0000 This register ...

Page 245: ...H 11 0 rw Bits Fields Descriptions 31 28 Reserved Must be kept at reset value 27 16 DAC1_DH 11 0 DAC1 12 bit right aligned data These bits specify the data that is to be converted by DAC1 15 12 Reserved Must be kept at reset value 11 0 DAC0_DH 11 0 DAC0 12 bit right aligned data These bits specify the data that is to be converted by DAC0 12 4 10 DAC concurrent mode 12 bit left aligned data holding...

Page 246: ...his register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DAC1_DH 7 0 DAC0_DH 7 0 rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 8 DAC1_DH 7 0 DAC1 8 bit right aligned data These bits specify the MSB 8 bit of the data that is to be converted by DAC1 7 0 DAC0_DH 7 0 DAC0 8 bit right ali...

Page 247: ...converted by DAC0 12 4 13 DAC1 data output register DAC1_DO Address offset 0x30 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DAC1_DO 11 0 r Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 DAC1_DO 11 0 DAC1 data output These bits which are read ...

Page 248: ...on the FWDGT can operate even if the main clock fails It s suitable for the situation that requires an independent environment and lower timing accuracy The free watchdog timer causes a reset when the internal down counter reaches 0 The register write protection function in free watchdog can be enabled to prevent it from changing the configuration unexpectedly 13 1 2 Characteristics Free running 1...

Page 249: ... software should reload the counter before the counter reaches 0x000 The FWDGT_PSC register and the FWDGT_RLD register are write protected Before writing these registers the software should write the value 0x5555 to the FWDGT_CTL register These registers will be protected again by writing any other value to the FWDGT_CTL register When an update operation of the prescaler register FWDGT_PSC or the ...

Page 250: ...interval must be inserted in the middle of reload and deepsleep standby mode commands by software setting For all the 101 devices and the 103 devices with flash no more than 128K when software finished the executing operation of FWDGT if the MCU needs enter the deepsleep standby mode immediately it is at least 100 us interval left between the two instructions For all the 101 devices and the 103 de...

Page 251: ...nd FWDGT_RLD write protection 0xCCCC Start the free watchdog counter When the counter reduces to 0 the free watchdog generates a reset 0xAAAA Reload the counter Prescaler register FWDGT_PSC Address offset 0x04 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 252: ... 7 6 5 4 3 2 1 0 Reserved RLD 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 RLD 11 0 Free watchdog timer counter reload value Write 0xAAAA in the FWDGT_CTL register will reload the FWDGT counter with the RLD value These bits are write protected Write 0x5555 in the FWDGT_CTL register before writing these bits During a write operation to this register the RUD bit i...

Page 253: ...value 1 RUD Free watchdog timer counter reload value update During a write operation to FWDGT_RLD register this bit is set and the value read from FWDGT_RLD register is invalid This bit is reset by hardware after the update operation of FWDGT_RLD register 0 PUD Free watchdog timer prescaler value update During a write operation to FWDGT_PSC register this bit is set and the value read from FWDGT_PS...

Page 254: ...dog timer clock is prescaled from the APB1 clock The window watchdog timer is suitable for the situation that requires an accurate timing 13 2 2 Characteristics Programmable free running 7 bit downcounter Generate reset in two conditions when WWDGT is enabled Reset when the counter reached 0x3F The counter is refreshed when the value of the counter is greater than the window register value Early w...

Page 255: ...WIN 6 0 bits in the configuration register WWDGT_CFG specifies the window value The software can prevent the reset event by reloading the downcounter when counter value is less than the window value and greater than 0x3F otherwise the watchdog causes a reset The early wakeup interrupt EWI is enabled by setting the EWIE bit in the WWDGT_CFG register and the interrupt is generated when the counter r...

Page 256: ...sured in ms Refer to Table 13 2 Min max timeout value at 54 MHz fPCLK1 for the minimum and maximum values of the tWWDGT Table 13 2 Min max timeout value at 54 MHz fPCLK1 Prescaler divider PSC 1 0 Min timeout value CNT 6 0 0x40 Max timeout value CNT 6 0 0x7F 1 1 00 75 8 μs 4 8 ms 1 2 01 151 7 μs 9 7 ms 1 4 10 303 4 μs 19 4 ms 1 8 11 606 8 μs 38 8 ms If the WWDGT_HOLD bit in DBG module is cleared th...

Page 257: ...hdog timer disabled 1 Window watchdog timer enabled 6 0 CNT 6 0 The value of the watchdog timer counter A reset occurs when the value of this counter decreases from 0x40 to 0x3F When the value of this counter is greater than the window value writing this counter also causes a reset Configuration register WWDGT_CFG Address offset 0x04 Reset value 0x0000 007F This register can be accessed by half wo...

Page 258: ...he value of the watchdog counter is greater than the Window value Status register WWDGT_STAT Address offset 0x08 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EWIF rw Bits Fields Descriptions 31 1 Reserved Must be kept at reset value 0 EWIF Early wakeup...

Page 259: ... least 4 times slower than the PCLK1 clock RTC clock source HXTAL clock divided by 128 LXTAL oscillator clock IRC40K oscillator clock Maskable interrupt source Alarm interrupt Second interrupt Overflow interrupt 14 3 Function overview The RTC circuits consist of two major units APB interface located in PCLK1 clock domain and RTC core located in RTC clock domain APB Interface is connected with the ...

Page 260: ...able access to the backup registers and RTC by setting the BKPWEN bit in the PMU_CTL 14 3 2 RTC reading The APB interface and RTC core are located in two different power supply domains In the RTC core only counter and divider registers are readable registers And the values in the two registers and the RTC flags are internally updated at each rising edge of the RTC clock which is resynchronized by ...

Page 261: ...n the RTC_CTL register sets to 1 14 3 4 RTC flag assertion Before the update of the RTC Counter the RTC second interrupt flag SCIF is asserted on the last RTCCLK cycle Before the counter equal to the RTC Alarm value which stored in the Alarm register increases by one the RTC Alarm interrupt flag ALRMIF is asserted on the last RTCCLK cycle Before the counter equals to 0x0 the RTC Overflow interrupt...

Page 262: ...62 Figure 14 3 RTC second and overflow waveform example RTC_PSC 3 RTC_ Overflow FFFFFFFD FFFFFFFE FFFFFFFF 0 1 RTC_Second RTC_ CNT OVIF RTC_PSC OVIF flag can be cleared by software RTCCLK 2 3 1 0 3 1 1 3 3 2 1 0 2 0 2 0 2 1 ...

Page 263: ...rved Must be kept at reset value 2 OVIE Overflow interrupt enable 0 Disable overflow interrupt 1 Enable overflow interrupt 1 ALRMIE Alarm interrupt enable 0 Disable alarm interrupt 1 Enable alarm interrupt 0 SCIE Second interrupt enable 0 Disable second interrupt 1 Enable second interrupt 14 4 2 RTC control register RTC_CTL Address offset 0x04 Reset value 0x0020 This register can be accessed by ha...

Page 264: ... in RTC_INTEN 1 ALRMIF Alarm interrupt flag 0 Alarm event not detected 1 Alarm event detected An interrupt named RTC global interrupt will occur if the ALRMIE bit is set in RTC_INTEN And another interrupt named the RTC Alarm interrupt will occur if the EXTI 17 is enabled in interrupt mode 0 SCIF Second interrupt flag 0 Second event not detected 1 Second event detected An interrupt will occur if th...

Page 265: ...lds Descriptions 31 16 Reserved Must be kept at reset value 15 0 PSC 15 0 RTC prescaler value low The frequency of SC_CLK is the RTCCLK frequency divided by PSC 19 0 1 14 4 5 RTC divider high register RTC_DIVH Address offset 0x10 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4...

Page 266: ...updated 14 4 7 RTC counter high register RTC_CNTH Address offset 0x18 Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 31 16 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CNT 31 16 RTC counter value high 14 4 8 RTC counter low register ...

Page 267: ... 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ALRM 31 16 w Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 ALRM 31 16 RTC alarm value high 14 4 10 RTC alarm low register RTC_ALRML Address offset 0x24 Reset value 0xFFFF This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4...

Page 268: ...0 TIMER0_TRGO ITI1 TIMER1_TRGO ITI2 TIMER3_TRGO ITI3 TIMER4_TRGO 2 TIMER1 ITI0 TIMER0_TRGO ITI1 refer to note 5 ITI2 TIMER2_TRGO ITI3 TIMER3_TRGO TIMER2 ITI0 TIMER0_TRGO ITI1 TIMER1_TRGO ITI2 TIMER4_TRGO ITI3 TIMER3_TRGO TIMER3 ITI0 TIMER0_TRGO ITI1 TIMER1_TRGO ITI2 TIMER2_TRGO ITI3 TIMER7_TRGO TIMER4 ITI0 TIMER1_TRGO ITI1 TIMER2_TRGO ITI2 TIMER3_TRGO ITI3 TIMER7_TRGO 3 TIMER8 ITI0 TIMER1_TRGO ITI...

Page 269: ...ts Source of counter clock is selectable internal clock internal trigger external input external trigger Multiple counter modes count up count down count up down Quadrature Decoder used for motion tracking and determination of both rotation direction and position Hall sensor for 3 phase motor control Programmable prescaler 16 bits The factor can be changed on the go Each channel is user configurab...

Page 270: ...rupt break update trig ctrl cap cmt CH1_O CH1_ON CH2_O CH2_ON CH3_O req en direct req set PSC PSC_CLK TIMER_CK ETIFP 15 1 4 Function overview Clock source configuration The advanced timer has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC TIMERx_SMCFG bit 2 0 SMC 2 0 3 b000 Internal clock CK_TIMER is selected as timer clock source which is fro...

Page 271: ...clock mode 1 External input ETI is selected as timer clock source ETI The TIMER_CK which drives counter s prescaler to count can be triggered by the event of rising or falling edge on the external pin ETI This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1 The other way to select the ETI signal as the clock source is to set the SMC 2 0 to 0x7 and the TRGS 2 0 to 0x7...

Page 272: ...nerated after TIMERx_CREP 1 times of overflow events The counting direction bit DIR in the TIMERx_CTL0 register should be set to 0 for the up counting mode Whenever if the update event software trigger is enabled by setting the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event If set the UPDIS bit in TIMERx_CTL0 register the update event ...

Page 273: ...K 8 PSC_CLK 97 98 99 0 1 Figure 15 5 Timing chart of up counting mode change TIMERx_CAR ongoing TIMER_CK CEN PSC_CLK CNT_REG 94 95 96 97 98 99 0 1 2 3 4 5 6 7 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule CNT_REG 113 114 115 116 117 118 119 120 0 1 2 98 99 0 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule 120 99 Au...

Page 274: ... the counter value will be initialized to the counter reload value and generates an update event If set the UPDIS bit in TIMERx_CTL0 register the update event is disabled When an update event occurs all the shadow registers repetition counter counter auto reload register prescaler register are updated Figure 15 6 Timing chart of down counting mode PSC 0 2 and Figure 15 7 Timing chart of down count...

Page 275: ...btract 1 in the up counting direction and generates an underflow event when the counter counts to 1 in the down counting direction The counting direction bit DIR in the TIMERx_CTL0 register is read only and indicates the counting direction when in the center aligned mode Setting the UPG bit in the TIMERx_SWEVG register will initialize the counter value to 0 and generates an update event irrespecti...

Page 276: ...F CHxCV 2 2 1 2 Update event from overflow underflow rate configuration The rate of update events generation from overflow and underflow events can be configured by the TIMERx_CREP register Counter repetition is used to generator update event or updates the timer registers only after a given number N 1 of cycles of the counter where N is CREP in TIMERx_CREP register The repetition counter is decre...

Page 277: ... the next update event occurs on overflow after writing an odd number to CREP then the subsequent update events will be generated on the overflow Figure 15 9 Repetition counter timing chart of center aligned counting mode CEN 3 2 1 0 1 2 98 99 98 2 1 0 Underflow Overflow TIMERx_CREP 0x0 TIMER_CK 1 2 98 99 98 2 UPIF TIMERx_CREP 0x1 1 0 1 2 98 99 98 97 UPIF UPIF TIMERx_CREP 0x2 PSC_CLK Figure 15 10 ...

Page 278: ... channel is built around a channel capture compare register including an input stage channel controller and an output stage Channel input capture function Channel input capture function allows the channel to perform measurements such as pulse timing frequency period duty cycle and so on The input stage consists of a digital filter a channel polarity selection edge detection and a channel prescaler...

Page 279: ...her channel and trig controlled by CHxMS The IC_prescaler make several the input event generate one effective capture event On the capture event CHxVAL will restore the value of Counter So the process can be divided to several steps as below Step1 Filter configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the input signal and requested signal quality configure compatible CHxCAPFLT Step2 Edge selecti...

Page 280: ...ut compare function Figure 15 13 channel output compare principle with complementary output x 0 1 2 Capture compare register CHxCV Counter output comparator Compare output control CHxCOMCTL CNT CHxCV CNT CHxCV CNT CHxCV Output complementary protection register Dead Time Output enable and polarity selector CHxP CHxNP CHxE CHxNE OxCPRE CHx_O CHx_ON Figure 15 14 channel output compare principle CH3_O...

Page 281: ...imed pulses with programmable position polarity duration and frequency When the counter matches the value in the TIMERx_CHxCV register of an output compare channel the channel n output can be set cleared or toggled based on CHxCOMCTL When the counter reaches the value in the TIMERx_CHxCV register the CHxIF bit is set and the channel n interrupt is generated if CHxIE 1 And the DMA request will be a...

Page 282: ...on the counter mode we can also divide PWM into EAPWM Edge aligned PWM and CAPWM Centre aligned PWM The EAPWM period is determined by TIMERx_CAR and duty cycle is determined by TIMERx_CHxCV Figure 15 16 Timing chart of EAPWM shows the EAPWM output and interrupts waveform The CAPWM period is determined by 2 TIMERx_CAR and duty cycle is by 2 TIMERx_CHxCV Figure 15 17 Timing chart of CAPWM shows the ...

Page 283: ...M 2 b01 down only CAM 2 b10 up only CHxIF CAM 2 b11 up down CHxIF Channel output prepare signal When the TIMERx is used in the compare match output mode the OxCPRE signal Channel x Output prepare signal is defined by setting the CHxCOMCTL filed The OxCPRE signal has several types of output function These include keeping the original level by setting the CHxCOMCTL field to 0x00 set to 1 by setting ...

Page 284: ...active active level irrespective of the comparison condition between the counter and the TIMERx_CHxCV values The OxCPRE signal can be forced to 0 when the ETIFP signal is derived from the external ETI pin and when it is set to a high level by setting the CHxCOMCEN bit to 1 in the TIMERx_CHCTL0 register The OxCPRE signal will not return to its active level until the next update event occurs Channel...

Page 285: ...Hx_ON output enable 1 0 CHx_O OxCPRE CHxP CHx_O output enable CHx_ON LOW CHx_ON output disable 1 CHx_O OxCPRE CHxP CHx_O output enable CHx_ON OxCPRE CHxNP CHx_ON output enable 1 0 0 CHx_O CHxP CHx_O output disable CHx_ON CHxNP CHx_ON output disable 1 CHx_O CHxP CHx_O output enable CHx_ON OxCPRE CHxNP CHx_ON output enable 1 0 CHx_O OxCPRE CHxP CHx_O output enable CHx_ON CHxNP CHx_ON output enable 1...

Page 286: ...always the inactive value as show in the Figure 15 18 Channel output complementary PWM with dead time insertion Figure 15 18 Channel output complementary PWM with dead time insertion 0 CHxVAL CAR CxOPRE CHx_O CHx_ON Deadtime Corner case Deadtime pulse width CHx_O CHx_ON Deadtime Pulse width Deadtime A B Break mode In this mode the output CHx_O and CHx_ON are controlled by the POEN IOS and ROS bits...

Page 287: ... CHxNP 0 ISOx ISOxN Quadrature decoder The quadrature decoder function uses two quadrature inputs CI0FE0 and CI1FE1 derived from the TIMERx_CH0 and TIMERx_CH1 pins respectively to interact to control the counter value The DIR bit is modified during each input source transition The counter can be changed by the edges of CI0FE0 only CI1FE1 only or both CI0FE0 and CI1FE1 the selection mode by setting...

Page 288: ... 1 Down Up X X CI1FE1 0 Up Down X X CI0FE0 1 X X Up Down CI0FE0 0 X X Down Up Note means no counting X means impossible 0 means low level 1 means high level Figure 15 20 Counter behavior with CI0FE0 polarity non inverted in mode 2 CI0FE0 CI1FE1 CNT_REG 21 20 22 23 24 25 24 23 22 21 20 19 TIMERx_CAR 99 Figure 15 21 Counter behavior with CI0FE0 polarity inverted in mode 2 CI0FE0 CI1FE1 CNT_REG 19 20...

Page 289: ... from Advanced GeneralL0 TIMER And TIMER_out need have functions of complementary and Dead time so only advanced timer can be chosen Else based on the timers internal connection relationship pair s timers can be selected For example TIMER_in TIMER0 TIMER_out TIMER7 ITI0 TIMER_in TIMER1 TIMER_out TIMER0 ITI1 And so on After getting appropriate timers combination and wire connection we need to confi...

Page 290: ...de the pause mode and the event mode which is selected by the SMC 2 0 in the TIMERx_SMCFG register The trigger input of these modes can be selected by the TRGS 2 0 in the TIMERx_SMCFG register Table 15 4 Examples of slave mode Mode Selection Source Selection Polarity Selection Filter and Prescaler LIST SMC 2 0 3 b100 restart mode 3 b101 pause mode 3 b110 event mode TRGS 2 0 000 ITI0 001 ITI1 010 I...

Page 291: ...unter will be cleared and restart when a rising edge of trigger input comes TRGS 2 0 3 b000 ITI0 is selected For ITI0 no polarity selector can be used For the ITI0 no filter and prescaler can be used Figure 15 24 Restart mode TIMER_CK CEN CNT_REG 94 95 96 97 98 99 0 1 2 3 4 0 1 2 UPIF ITI0 TRGIF Internal sync delay Exam2 Pause mode The counter will be paused when the trigger input is low and it wi...

Page 292: ...SPM in TIMERx_CTL0 When you set SPM the counter will be clear and stop when the next update event In order to get pulse waveform you can set the TIMERx to PWM mode or compare by CHxCOMCTL Once the timer is set to operate in the single pulse mode it is not necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter The trigger to generate a pulse can be sourced ...

Page 293: ...in the PWM0 or PWM1 output mode and the trigger source is derived from the trigger signal Figure 15 27 Single pulse mode TIMERx_CHxCV 4 TIMERx_CAR 99 shows an example Figure 15 27 Single pulse mode TIMERx_CHxCV 4 TIMERx_CAR 99 TIMER_CK PSC_CLK CEN CNT_REG 0 1 2 3 4 5 98 99 00 OxCPRE CI3 Under SPM counter stop Timers interconnection Timer can be configured as interconnection that is one timer which...

Page 294: ...nput trigger Table 15 6 Ouput trigger of Timer0 and Timer7 shows the output trigger Table 15 5 Input trigger of Timer0 and Timer7 ITI0 ITI1 ITI2 ITI3 TIMER0 TIMER4_TRGO TIMER1_TRGO TIMER2_TRGO TIMER3_TRGO TIMER7 TIMER0_TRGO TIMER1_TRGO TIMER3_TRGO TIMER4_TRGO Table 15 6 Ouput trigger of Timer0 and Timer7 TIMER0_TRGO TIMER7_TRGO TIMER1 ITI0 TIMER2 ITI0 TIMER3 ITI0 ITI3 TIMER4 ITI3 TIMER7 ITI0 Note ...

Page 295: ...internal clock after trigger by Timer2 enable output When Timer0 receives the trigger signal its CEN bit is set and the counter counts until we disable timer0 In this example both counter clock frequencies are divided by 3 by the prescaler compared to TIMER_CK fCNT_CLK fTIMER_CK 3 Timer0 s SMC is set as event mode so Timer0 can not be disabled by Timer2 s disable signal Do as follow 1 Configure Ti...

Page 296: ...timer s counters start counting synchronously on the internal clock and both TRGIF flags are set Figure 15 30 Triggering TIMER0 and TIMER2 with TIMER2 s CI0 input TIMER_CK CNT_REG CNT_REG CI0 00 01 CEN 02 03 00 01 02 03 CNT_CK TRGIF CEN TRGIF TIMER2 TIMER0 Timer DMA mode Timer s DMA mode is the function that configures timer s register by DMA module The relative registers are TIMERx_DMACFG and TIM...

Page 297: ...ss timer s registers DMATA 0x4 DMATA 0x8 DMATA 0xc at the next 3 accesses to TIMERx_DMATB In one word one time DMA internal interrupt event assert DMATC 1 times request will be send by TIMERx If one more time DMA request event coming TIMERx will repeat the process as above Timer debug mode When the Cortex M3 halted and the TIMERx_HOLD configuration bit in DBG_CTL register is set to 1 the TIMERx co...

Page 298: ..._TIMER 2 10 fDTS fCK_TIMER 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter aligns mode selection 00 No center aligned mode edge aligned mode The direction of the counter is specified by the DIR bit 01 Center aligned and counting down assert mode The counter counts u...

Page 299: ...vent 1 This event generates update interrupts or DMA requests The counter generates an overflow or underflow event 1 UPDIS Update disable This bit is used to enable or disable the update event generation 0 Update event enable When an update event occurs the corresponding shadow registers are loaded with their preloaded values These events generate update event The UPG bit is set The counter genera...

Page 300: ...t CH0_ON is set low 1 When POEN bit is reset CH0_ON is set high This bit can be modified only when PROT 1 0 bits in TIMERx_CCHP register is 00 8 ISO0 Idle state of channel 0 output 0 When POEN bit is reset CH0_O is set low 1 When POEN bit is reset CH0_O is set high The CH0_O output changes after a dead time if CH0_ON is implemented This bit can be modified only when PROT 1 0 bits in TIMERx_CCHP re...

Page 301: ...n capture or compare event occurs the DMA request of channel x is sent 1 When update event occurs the DMA request of channel x is sent 2 CCUC Commutation control shadow register update control When the commutation control shadow enable for CHxEN CHxNEN and CHxCOMCTL bits are set CCSE 1 these shadow registers update are controlled as below 0 The shadow registers update by when CMTG bit is set 1 The...

Page 302: ...his case The clock source of the timer will be ETIFP if external clock mode 0 and external clock mode 1 are configured at the same time Note External clock mode 0 enable is in this register s SMC 2 0 bit filed 13 12 ETPSC 1 0 The prescaler of external trigger The frequency of external trigger signal ETIFP must not be at higher than 1 4 of TIMER_CK frequency When the external trigger signal is a fa...

Page 303: ...nected together 0 Master slave mode disable 1 Master slave mode enable 6 4 TRGS 2 0 Trigger selection This bit field specifies which signal is selected as the trigger input which is used to synchronize the counter 000 ITI0 001 ITI1 010 ITI2 011 ITI3 100 CI0F_ED 101 CI0FE0 110 CI1FE1 111 ETIFP These bits must not be changed when slave mode is enabled 3 Reserved Must be kept at reset value 2 0 SMC 2...

Page 304: ... the rising edges of the selected trigger DMA and interrupt enable register TIMERx_DMAINTEN Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRGDEN CMTDEN CH3DEN CH2DEN CH1DEN CH0DEN UPDEN BRKIE TRGIE CMTIE CH3IE CH2IE CH1IE CH0IE UPIE rw rw rw rw rw rw...

Page 305: ...nterrupt enable 0 disabled 1 enabled 4 CH3IE Channel 3 capture compare interrupt enable 0 disabled 1 enabled 3 CH2IE Channel 2 capture compare interrupt enable 0 disabled 1 enabled 2 CH1IE Channel 1 capture compare interrupt enable 0 disabled 1 enabled 1 CH0IE Channel 0 capture compare interrupt enable 0 disabled 1 enabled 0 UPIE Update interrupt enable 0 disabled 1 enabled Interrupt flag register...

Page 306: ...y been set This flag is cleared by software 0 No over capture interrupt occurred 1 Over capture interrupt occurred 8 Reserved Must be kept at reset value 7 BRKIF Break interrupt flag When the break input is inactive the bit is set by hardware When the break input is inactive the bit can be cleared by software 0 No active level break has been detected 1 An active level has been detected 6 TRGIF Tri...

Page 307: ...update event and cleared by software 0 No update interrupt occurred 1 Update interrupt occurred Software event generation register TIMERx_SWEVG Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BRKG TRGG CMTG CH3G CH2G CH1G CH0G UPG w w w w w w w w Bits ...

Page 308: ...on This bit is set by software in order to generate a capture or compare event in channel 0 it is automatically cleared by hardware When this bit is set the CH0IF flag is set the corresponding interrupt or DMA request is sent if enabled In addition if channel 1 is configured in input mode the current value of the counter is captured in TIMERx_CH0CV register and the CH0OF flag is set if the CH0IF f...

Page 309: ...election This bit field is writable only when the channel is not active CH1EN bit in TIMERx_CHCTL2 register is reset 00 Channel 1 is programmed as output mode 01 Channel 1 is programmed as input mode IS1 is connected to CI1FE1 10 Channel 1 is programmed as input mode IS1 is connected to CI0FE1 11 Channel 1 is programmed as input mode IS1 is connected to ITS Note When CH1MS 1 0 11 it is necessary t...

Page 310: ...n result changes This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 11 and CH0MS bit filed is 00 COMPARE MODE 3 CH0COMSEN Channel 0 compare output shadow enable When this bit is set the shadow register of TIMERx_CH0CV register which updates at each update event will be enabled 0 Channel 0 output compare shadow disable 1 Channel 0 output compare shadow enable The PWM mod...

Page 311: ...fer to CH0CAPPSC description 9 8 CH1MS 1 0 Channel 1 mode selection Same as Output compare mode 7 4 CH0CAPFLT 3 0 Channel 0 input capture filter control The CI0 input signal can be filtered by digital filter and this bit field configure the filtering capability Basic principle of digital filter continuously sample the CI0 input signal according to fSAMP and record the number of times of the same l...

Page 312: ...rved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH3COM CEN CH3COMCTL 2 0 CH3COM SEN CH3COM FEN CH3MS 1 0 CH2COM CEN CH2COMCTL 2 0 CH2COM SEN CH2COM FEN CH2MS 1 0 CH3CAPFLT 3 0 CH3CAPPSC 1 0 CH2CAPFLT 3 0 CH2CAPPSC 1 0 rw rw rw rw rw rw Output compare mode Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 CH3COMCEN Channel 3 output compare clear enable Refer to CH0COMCEN description...

Page 313: ...pare register TIMERx_CH2CV 010 Clear the channel output O2CPRE signal is forced low when the counter is equals to the output compare register TIMERx_CH2CV 011 Toggle on match O2CPRE toggles when the counter is equals to the output compare register TIMERx_CH2CV 100 Force low O2CPRE is forced to low level 101 Force high O2CPRE is forced to high level 110 PWM mode 0 When counting up O2CPRE is high wh...

Page 314: ... is programmed as output mode 01 Channel 2 is programmed as input mode IS2 is connected to CI2FE2 10 Channel 2 is programmed as input mode IS2 is connected to CI3FE2 11 Channel 2 is programmed as input mode IS2 is connected to ITS Note When CH2MS 1 0 11 it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register Input capture mode Bits Fields Descriptions 31 16 R...

Page 315: ...sable input capture occurs on every channel input edge 01 The input capture occurs on every 2 channel input edges 10 The input capture occurs on every 4 channel input edges 11 The input capture occurs on every 8 channel input edges 1 0 CH2MS 1 0 Channel 2 mode selection Same as Output compare mode Channel control register 2 TIMERx_CHCTL2 Address offset 0x20 Reset value 0x0000 0000 This register ha...

Page 316: ... function polarity Refer to CH0P description 4 CH1EN Channel 1 capture compare function enable Refer to CH0EN description 3 CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode this bit specifies the complementary output signal polarity 0 Channel 0 complementary output high level is active level 1 Channel 0 complementary output low level is active level This bi...

Page 317: ...t enables CH0_O signal in active state When channel 0 is configured in input mode setting this bit enables the capture event in channel0 0 Channel 0 disabled 1 Channel 0 enabled Counter register TIMERx_CNT Address offset 0x24 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 15 ...

Page 318: ... has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CARL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CARL 15 0 Counter auto reload value This bit filed specifies the auto reload value of the counter Note When the timer is configured in input capture mode this register must be configur...

Page 319: ...o be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH0VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH0VAL 15 0 Capture or compare value of channel0 When channel 0 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit ...

Page 320: ... capture compare value register TIMERx_CH2CV Address offset 0x3C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH2VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH2VAL 15 0 Capture or compare value of channel 2 When channel 2 is configured i...

Page 321: ...enabled the shadow register updates every update event Complementary channel protection register TIMERx_CCHP Address offset 0x44 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POEN OAEN BRKP BRKEN ROS IOS PROT 1 0 DTCFG 7 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 16 R...

Page 322: ... set this bit specifies the output state for the channels which has a complementary output and has been configured in output mode 0 When POEN bit is set the channel output signals CHx_O CHx_ON are disabled 1 When POEN bit is set the channel output signals CHx_O CHx_ON are enabled with relationship to CHxEN CHxNEN bits in TIMERx_CHCTL2 register This bit cannot be modified when PROT 1 0 bit filed in...

Page 323: ...0 Dead time configure The relationship between DTVAL value and the duration of dead time is as follow DTCFG 7 5 The duration of dead time 3 b0xx DTCFG 7 0 tDTS_CK 3 b10x 64 DTCFG 5 0 tDTS_CK 2 3 b110 32 DTCFG 4 0 tDTS_CK 8 3 b111 32 DTCFG 4 0 tDTS_CK 16 Note 1 tDTS_CK is the period of DTS_CK which is configured by CKDIV 1 0 in TIMERx_CTL0 2 This bit can be modified only when PROT 1 0 bit filed in ...

Page 324: ...tart address 0x4 DMA transfer buffer register TIMERx_DMATB Address offset 0x4C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMATB 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 DMATB 15 0 DMA transfer buffer When a read or write operation is as...

Page 325: ... width 16 bits Source of count clock is selectable internal clock internal trigger external input external trigger Multiple counter modes count up count down count up down Quadrature decoder used for motion tracking and determination of both rotation direction and position Hall sensor for 3 phase motor control Programmable prescaler 16 bits Factor can be changed on the go Each channel is user conf...

Page 326: ... TIMERx_TG TIMERx_UP PSC PSC_CLK TIMER_CK req en direct req set ETIFP 15 2 4 Function overview Clock source configuration The general level0 TIMER has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC TIMERx_SMCFG bit 2 0 SMC 2 0 3 b000 Internal timer clock CK_TIMER which is from module RCU The default internal clock source is the CK_TIMER used t...

Page 327: ...ock mode 1 External input is selected as timer clock source ETI The TIMER_CK driven counter s prescaler to count can be triggered by the event of rising or falling edge on the external pin ETI This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1 The other way to select the ETI signal as the clock source is set the SMC 2 0 to 0x7 and the TRGS 2 0 to 0x7 respectively N...

Page 328: ... is generated at each counter overflow The counting direction bit DIR in the TIMERx_CTL1 register should be set to 0 for the up counting mode When the update event is set by the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event If the UPDIS bit in TIMERx_CTL0 register is set the update event is disabled When an update event occurs all the...

Page 329: ...K 8 PSC_CLK 97 98 99 0 1 Figure 15 35 Timing chart of up counting mode change TIMERx_CAR ongoing TIMER_CK CEN PSC_CLK CNT_REG 94 95 96 97 98 99 0 1 2 3 4 5 6 7 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule CNT_REG 113 114 115 116 117 118 119 120 0 1 2 98 99 0 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule 120 99 A...

Page 330: ...to the counter reload value and generates an update event If the UPDIS bit in TIMERx_CTL0 register is set the update event is disabled When an update event occurs all the shadow registers counter auto reload register prescaler register are updated Figure 15 36 Timing chart of down counting mode PSC 0 2 and Figure 15 37 Timing chart of down counting mode change TIMERx_CAR ongoing show some examples...

Page 331: ...load value subtract 1 in the up counting mode and generates an underflow event when the counter counts to 1 in the down counting mode The counting direction bit DIR in the TIMERx_CTL0 register is read only and indicates the counting direction when in the center aligned mode Setting the UPG bit in the TIMERx_SWEVG register will initialize the counter value to 0 irrespective of whether the counter i...

Page 332: ...ly TIMERx_CTL0 CAM 2 b10 downcount only CHxIF CHxCV 2 2 1 2 Input capture and output compare channels The general level0 Timer has four independent channels which can be used as capture inputs or compare match outputs Each channel is built around a channel capture compare register including an input stage channel controller and an output stage Channel input capture function Channel input capture f...

Page 333: ...digital filter to generate a filtered input signal Then through the edge detector the rising and fall edge are detected You can select one of them by CHxP One more selector is for the other channel and trig controlled by CHxMS The IC_prescaler make several the input event generate one effective capture event On the capture event CHxVAL will restore the value of Counter So the process can be divide...

Page 334: ...ompare register CHxCV Counter output comparator Compare output control CHxCOMCTL Output enable and polarity selector CHxP CHxE OxCPRE CHx_O CNT CHxCV CNT CHxCV CNT CHxCV Figure 15 40 channel output compare principle x 0 1 2 3 shows the principle circuit of channels output compare function The relationship between the channel output signal CHx_O and the OxCPRE signal more details refer to Channel o...

Page 335: ...CHxCV About the CHxVAL you can change it on the go to meet the waveform you expected Step5 Start the counter by CEN Figure 15 41 Output compare in three modes show the three compare modes toggle set clear CAR 0x63 CHxVAL 0x3 Figure 15 41 Output compare in three modes CEN CNT_REG 00 01 02 03 04 05 62 63 Overflow match toggle CNT_CLK OxCPRE 00 01 02 03 04 05 62 63 01 02 03 04 05 00 match set match c...

Page 336: ...TIMERx_CAR and duty cycle is determined by 2 TIMERx_CHxCV Figure 15 43 CAPWM timechart shows the CAPWM output and interrupts waveform If TIMERx_CHxCV is greater than TIMERx_CAR the output will be always active under PWM mode0 CHxCOMCTL 3 b110 And if TIMERx_CHxCV is equal to zero the output will be always inactive under PWM mode0 CHxCOMCTL 3 b110 Figure 15 42 EAPWM timechart 0 CHxVAL CAR PWM MODE0 ...

Page 337: ... PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06 0x07 In these modes the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content With regard to a more detail description refer to the relative bit definition Another special function of...

Page 338: ... 3 b110 event mode TRGS 2 0 000 ITI0 001 ITI1 010 ITI2 011 ITI3 100 CI0F_ED 101 CI0FE0 110 CI1FE1 111 ETIFP If CI0FE0 or CI1FE1 is selected as the trigger source configure the CHxP and CHxNP for the polarity selection and inversion If ETIFP is selected as the trigger source configure the ETP for polarity selection and inversion For the ITIx no filter and prescaler can be used For the CIx filter ca...

Page 339: ...art when the trigger input is high TRGS 2 0 3 b101 CI0FE0 is selected TI0S 0 Non xor CH0P 0 CI0FE0 does not invert The capture event will occur on the rising edge only Filter is bypassed in this example Figure 15 45 Pause mode TIMER_CK CEN CNT_REG 94 95 96 97 98 CI0 TRGIF CI0FE0 99 Exam3 Event mode The counter will start to count when a rising edge of trigger input comes TRGS 2 0 3 b111 ETIFP is s...

Page 340: ...internal clock mode quadrature decoder mode restart mode pause mode event mode external clock mode Table 15 8 Input trigger of Timerx x 1 2 3 4 show the input trigger Table 15 9 Ouput trigger of Timerx x 1 2 3 4 show the output trigger Table 15 8 Input trigger of Timerx x 1 2 3 4 ITI0 ITI1 ITI2 ITI3 TIMER1 TIMER0_TRGO TIMER1TRGO1_REMAP Note TIMER2_TRGO TIMER3_TRGO TIMER2 TIMER0_TRGO TIMER1_TRGO TI...

Page 341: ...est to DMA which is configured to M2P mode and PADDR is TIMERx_DMATB then DMA will access the TIMERx_DMATB In fact register TIMERx_DMATB is only a buffer timer will map the TIMERx_DMATB to an internal register appointed by the field of DMATA in TIMERx_DMACFG If the field of DMATC in TIMERx_DMACFG is 0 1 transfer then the timer s DMA request is finished While if TIMERx_DMATC is not 0 such as 3 4 tr...

Page 342: ... specify division factor between the CK_TIMER and the dead time and digital filter sample clock DTS 00 fDTS fCK_TIMER 01 fDTS fCK_TIMER 2 10 fDTS fCK_TIMER 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter aligns mode selection 00 No center aligned mode edge aligned m...

Page 343: ...rrupts or DMA requests The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an update event 1 This event generates update interrupts or DMA requests The counter generates an overflow or underflow event 1 UPDIS Update disable This bit is used to enable or disable the update event generation 0 Update event enable When an update event occurs the correspon...

Page 344: ...source Master timer generate a reset the UPG bit in the TIMERx_SWEVG register is set 001 Enable When a conter start event occurs a TRGO trigger signal is output The counter start source CEN control bit is set The trigger input in pause mode is high 010 When an update event occurs a TRGO trigger signal is output The update source depends on UPDIS bit and UPS bit 011 When a capture or compare pulse ...

Page 345: ...for enable External clock mode1 In external clock mode 1 the counter is clocked by any active edge on the ETIFP signal 0 External clock mode 1 disabled 1 External clock mode 1 enabled When the slave mode is configured as restart mode pause mode or event mode the timer can still work in the external clock 1 mode by setting this bit But the TRGS bits must not be 3 b111 in this case The clock source ...

Page 346: ...as follows EXTFC 3 0 Times fSAMP 4 b0000 Filter disabled 4 b0001 2 fCK_TIMER 4 b0010 4 4 b0011 8 4 b0100 6 fDTS_CK 2 4 b0101 8 4 b0110 6 fDTS_CK 4 4 b0111 8 4 b1000 6 fDTS_CK 8 4 b1001 8 4 b1010 5 fDTS_CK 16 4 b1011 6 4 b1100 8 4 b1101 5 fDTS_CK 32 4 b1110 6 4 b1111 8 7 MSM Master slave mode This bit can be used to synchronize selected timers to begin counting at the same time The TRGI is used as ...

Page 347: ...date event is generated on the rising edge of the selected trigger input 101 Pause mode The trigger input enables the counter clock when it is high and disables the counter clock when it is low 110 Event mode A rising edge of the trigger input enables the counter 111 External clock mode 0 The counter counts on the rising edges of the selected trigger DMA and interrupt enable register TIMERx_DMAINT...

Page 348: ...d 8 UPDEN Update DMA request enable 0 disabled 1 enabled 7 Reserved Must be kept at reset value 6 TRGIE Trigger interrupt enable 0 disabled 1 enabled 5 Reserved Must be kept at reset value 4 CH3IE Channel 3 capture compare interrupt enable 0 disabled 1 enabled 3 CH2IE Channel 2 capture compare interrupt enable 0 disabled 1 enabled 2 CH1IE Channel 1 capture compare interrupt enable 0 disabled 1 ena...

Page 349: ...re flag Refer to CH0OF description 9 CH0OF Channel 0 over capture flag When channel 0 is configured in input mode this flag is set by hardware when a capture event occurs while CH0IF flag has already been set This flag is cleared by software 0 No over capture interrupt occurred 1 Over capture interrupt occurred 8 7 Reserved Must be kept at reset value 6 TRGIF Trigger interrupt flag This flag is se...

Page 350: ... Software event generation register TIMERx_SWEVG Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRGG Reserved CH3G CH2G CH1G CH0G UPG w w w w w w Bits Fields Descriptions 31 7 Reserved Must be kept at reset value 6 TRGG Trigger event generation This b...

Page 351: ...ed by hardware automatically When this bit is set the counter is cleared if the center aligned or up counting mode is selected else down counting it takes the auto reload value The prescaler counter is cleared at the same time 0 No generate an update event 1 Generate an update event Channel control register 0 TIMERx_CHCTL0 Address offset 0x18 Reset value 0x0000 0000 This register has to be accesse...

Page 352: ... of the the output prepare signal O0CPRE In addition the high level of O0CPRE is the active level and CH0_O and CH0_ON channels polarity depends on CH0P and CH0NP bits 000 Timing mode The O0CPRE signal keeps stable independent of the comparison between the register TIMERx_CH0CV and the counter TIMERx_CNT 001 Set the channel output O0CPRE signal is forced high when the counter is equals to the outp...

Page 353: ... Channel 0 I O mode selection This bit field specifies the work mode of the channel and the input signal selection This bit field is writable only when the channel is not active CH0EN bit in TIMERx_CHCTL2 register is reset 00 Channel 0 is programmed as output mode 01 Channel 0 is programmed as input mode IS0 is connected to CI0FE0 10 Channel 0 is programmed as input mode IS0 is connected to CI1FE0...

Page 354: ... 32 4 b1110 6 4 b1111 8 3 2 CH0CAPPSC 1 0 Channel 0 input capture prescaler This bit field specifies the factor of the prescaler on channel 0 input The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear 00 Prescaler disable input capture occurs on every channel input edge 01 The input capture occurs on every 2 channel input edges 10 The input capture occurs on every 4 channel inp...

Page 355: ...mode 01 Channel 3 is programmed as input mode IS3 is connected to CI3FE3 10 Channel 3 is programmed as input mode IS3 is connected to CI2FE3 11 Channel 3 is programmed as input mode IS3 is connected to ITS Note When CH3MS 1 0 11 it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register 7 CH2COMCEN Channel 2 output compare clear enable When this bit is set if th...

Page 356: ...be enabled 0 Channel 2 output compare shadow disable 1 Channel 2 output compare shadow enable The PWM mode can be used without verifying the shadow register only in single pulse mode when SPM 1 2 CH2COMFEN Channel 2 output compare fast enable When this bit is set the effect of an event on the trigger in input on the capture compare output will be accelerated if the channel is configured in PWM1 or...

Page 357: ...g the filtering capacity configured by this bit it is considered to be an effective level The filtering capability configuration is as follows CH2CAPFLT 3 0 Times fSAMP 4 b0000 Filter disabled 4 b0001 2 fCK_TIMER 4 b0010 4 4 b0011 8 4 b0100 6 fDTS 2 4 b0101 8 4 b0110 6 fDTS 4 4 b0111 8 4 b1000 6 fDTS 8 4 b1001 8 4 b1010 5 fDTS 16 4 b1011 6 4 b1100 8 4 b1101 5 fDTS 32 4 b1110 6 4 b1111 8 3 2 CH2CAP...

Page 358: ...ion enable Refer to CH0EN description 11 10 Reserved Must be kept at reset value 9 CH2P Channel 2 capture compare function polarity Refer to CH0P description 8 CH2EN Channel 2 capture compare function enable Refer to CH0EN description 7 6 Reserved Must be kept at reset value 5 CH1P Channel 1 capture compare function polarity Refer to CH0P description 4 CH1EN Channel 1 capture compare function enab...

Page 359: ...isabled 1 Channel 0 enabled Counter register TIMERx_CNT Address offset 0x24 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CNT 15 0 This bit filed indicates the current counter value Writing to t...

Page 360: ...23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CARL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CARL 15 0 Counter auto reload value This bit filed specifies the auto reload value of the counter Note When the timer is configured in input capture mode this register must be configured a non zero value such as 0xFFFF which is larger than use...

Page 361: ...ord 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH1VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH1VAL 15 0 Capture or compare value of channel1 When channel 1 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only...

Page 362: ... This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH3VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH3VAL 15 0 Capture or compare value of channel 3 When channel3 is configured in input mode this bit filed indicates the counter value corresponding to the last capture...

Page 363: ...MERx_DMA address first time this bit field specifies the address you just access And then the second access to the TIMERx_DMATB you will access the address of start address 0x4 DMA transfer buffer register TIMERx_DMATB Address offset 0x4C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 ...

Page 364: ...counters incrementing in unison The general level1 timer module Timer8 11 is available only in the GD32F10x_XD devices 15 3 2 Characteristics Total channel num 2 Counter width 16 bits Source of count clock is selectable internal clock internal trigger external input external trigger Multiple counter modes count up count down count up down Programmable prescaler 16 bits Factor can be changed on the...

Page 365: ...on overview Clock source configuration The advanced timer has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC TIMERx_SMCFG bit 2 0 SMC 2 0 3 b000 Internal clock CK_TIMER is selected as timer clock source which is from module RCU The default clock source is the CK_TIMER for driving the counter prescaler when the SMC 2 0 3 b000 When the CEN is se...

Page 366: ... falling edge on the external pin TIMERx_CH0 TIMERx_CH1 This mode can be selected by setting SMC 2 0 to 0x7 and the TRGS 2 0 to 0x4 0x5 or 0x6 And the counter prescaler can also be driven by rising edge on the internal trigger input pin ITI0 1 2 3 This mode can be selected by setting SMC 2 0 to 0x7 and the TRGS 2 0 to 0x0 0x1 0x2 or 0x3 Clock prescaler The counter clock PSC_CK is obtained by the T...

Page 367: ... is generated at each counter overflow The counting direction bit DIR in the TIMERx_CTL1 register should be set to 0 for the up counting mode When the update event is set by the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event If the UPDIS bit in TIMERx_CTL0 register is set the update event is disabled When an update event occurs all the...

Page 368: ...K 8 PSC_CLK 97 98 99 0 1 Figure 15 51 Timing chart of up counting mode change TIMERx_CAR ongoing TIMER_CK CEN PSC_CLK CNT_REG 94 95 96 97 98 99 0 1 2 3 4 5 6 7 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule CNT_REG 113 114 115 116 117 118 119 120 0 1 2 98 99 0 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule 120 99 A...

Page 369: ...ized to the counter reload value and generates an update event If set the UPDIS bit in TIMERx_CTL0 register the update event is disabled When an update event occurs all the shadow registers counter auto reload register prescaler register are updated Figure 15 52 Timing chart of down counting mode PSC 0 2 and Figure 15 53 Timing chart of down counting mode change TIMERx_CAR ongoing show some exampl...

Page 370: ...r reload value subtract 1 in the up counting direction and generates an underflow event when the counter counts to 1 in the down counting direction The counting direction bit DIR in the TIMERx_CTL0 register is read only and indicates the counting direction when in the center aligned mode Setting the UPG bit in the TIMERx_SWEVG register will initialize the counter value to 0 and generates an update...

Page 371: ... 2 Input capture and output compare channels The general level1 timer has two independent channels which can be used as capture inputs or compare match outputs Each channel is built around a channel capture compare register including an input stage channel controller and an output stage Channel input capture function Channel input capture function allows the channel to perform measurements such as...

Page 372: ...d You can select one of them by CHxP One more selector is for the other channel and trig controlled by CHxMS The IC_prescaler make several the input event generate one effective capture event On the capture event CHxVAL will restore the value of Counter So the process can be divided to several steps as below Step1 Filter configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the input signal and reques...

Page 373: ...ounter output comparator Compare output control CHxCOMCTL Output enable and polarity selector CHxP CHxE OxCPRE CHx_O CNT CHxCV CNT CHxCV CNT CHxCV Figure 15 56 channel output compare principle x 0 1 shows the principle circuit of channels output compare function The relationship between the channel output signal CHx_O and the OxCPRE signal more details refer to Channel output prepare signal is des...

Page 374: ...ation by TIMERx_CAR and TIMERx_CHxCV About the CHxVAL you can change it on the go to meet the waveform you expected Step5 Start the counter by CEN The timechart below show the three compare modes toggle set clear CAR 0x63 CHxVAL 0x3 Figure 15 57 Output compare under three modes CEN CNT_REG 00 01 02 03 04 05 62 63 Overflow match toggle CNT_CLK OxCPRE 00 01 02 03 04 05 62 63 01 02 03 04 05 00 match ...

Page 375: ...m The CAPWM period is determined by 2 TIMERx_CAR and duty cycle is determined by 2 TIMERx_CHxCV Figure 15 59 CAPWM timechart shows the CAPWM output and interrupt waveform If TIMERx_CHxCV is greater than TIMERx_CAR the output will be always active under PWM mode0 CHxCOMCTL 3 b110 And if TIMERx_CHxCV is equal to zero the output will be always inactive under PWM mode0 CHxCOMCTL 3 b110 Figure 15 58 EA...

Page 376: ...counter value matches the content of the TIMERx_CHxCV register The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06 0x07 In these modes the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content With regard to a more detail descriptio...

Page 377: ... CI1FE1 111 Reserved If CI0FE0 or CI1FE1 is selected as the trigger source configure the CHxP and CHxNP for the polarity selection and inversion For the ITIx no filter and prescaler can be used For the CIx filter can be used by configuring CHxCAPFLT no prescaler can be used Exam1 Restart mode The counter will be cleared and restart when a rising edge of trigger input comes TRGS 2 0 3 b000 ITI0 is ...

Page 378: ... 97 TRGIF CI0FE0 Single pulse mode Single pulse mode is opposite to the repetitive mode which can be enabled by setting SPM in TIMERx_CTL0 When you set SPM the counter will be clear and stop when the next update event In order to get pulse waveform you can set the TIMERx to PWM mode or compare by CHxCOMCTL Once the timer is set to operate in the single pulse mode it is not necessary to set the tim...

Page 379: ...figured to operate in the PWM0 or PWM1 output mode and the trigger source is derived from the trigger signal Figure 15 63 Single pulse mode TIMERx_CHxCV 4 TIMERx_CAR 99 shows an example Figure 15 63 Single pulse mode TIMERx_CHxCV 4 TIMERx_CAR 99 TIMER_CK PSC_CLK CEN CNT_REG 0 1 2 3 4 5 98 99 00 OxCPRE CI1 Under SPM counter stop Timers interconnection Timer can be configured as interconnection that...

Page 380: ...GD32F10x User Manual 380 Timer debug mode When the Cortex M3 halted and the TIMERx_HOLD configuration bit in DBG_CTL register set to 1 the TIMERx counter stops ...

Page 381: ..._TIMER 2 10 fDTS fCK_TIMER 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter aligns mode selection 00 No center aligned mode edge aligned mode The direction of the counter is specified by the DIR bit 01 Center aligned and counting down assert mode The counter counts u...

Page 382: ...his event generates update interrupts or DMA requests The counter generates an overflow or underflow event 1 UPDIS Update disable This bit is used to enable or disable the update event generation 0 Update event enable When an update event occurs the corresponding shadow registers are loaded with their preloaded values These events generate update event The UPG bit is set The counter generates an o...

Page 383: ...ynchronize the counter 000 ITI0 001 ITI1 010 ITI2 011 ITI3 100 CI0F_ED 101 CI0FE0 110 CI1FE1 111 Reserved These bits must not be changed when slave mode is enabled 3 Reserved Must be kept at reset value 2 0 SMC 2 0 Slave mode control 000 Disable mode The slave mode is disabled The prescaler is clocked directly by the internal clock TIMER_CK when CEN bit is set high 001 Reserved 010 Reserved 011 Re...

Page 384: ...escriptions 31 7 Reserved Must be kept at reset value 6 TRGIE Trigger interrupt enable 0 disabled 1 enabled 5 3 Reserved Must be kept at reset value 2 CH1IE Channel 1 capture compare interrupt enable 0 disabled 1 enabled 1 CH0IE Channel 0 capture compare interrupt enable 0 disabled 1 enabled 0 UPIE Update interrupt enable 0 disabled 1 enabled Interrupt flag register TIMERx_INTF Address offset 0x10...

Page 385: ... When in pause mode both edges on trigger input generates a trigger event otherwise only an active edge on trigger input can generates a trigger event 0 No trigger event occurred 1 Trigger interrupt occurred 5 3 Reserved Must be kept at reset value 2 CH1IF Channel 1 s capture compare interrupt flag Refer to CH0IF description 1 CH0IF Channel 0 s capture compare interrupt flag This flag is set by ha...

Page 386: ...ation This bit is set by software in order to generate a capture or compare event in channel 0 it is automatically cleared by hardware When this bit is set the CH1IF flag is set the corresponding interrupt or DMA request is sent if enabled In addition if channel 1 is configured in input mode the current value of the counter is captured in TIMERx_CH0CV register and the CH0OF flag is set if the CH0I...

Page 387: ... not active CH1EN bit in TIMERx_CHCTL2 register is reset 00 Channel 1 is programmed as output mode 01 Channel 1 is programmed as input mode IS1 is connected to CI1FE1 10 Channel 1 is programmed as input mode IS1 is connected to CI0FE1 11 Channel 1 is programmed as input mode IS1 is connected to ITS Note When CH1MS 1 0 11 it is necessary to select an internal trigger input through TRGS bits in TIME...

Page 388: ...t is set the shadow register of TIMERx_CH0CV register which updates at each update event will be enabled 0 Channel 0 output compare shadow disable 1 Channel 0 output compare shadow enable The PWM mode can be used without verifying the shadow register only in single pulse mode when SPM 1 2 CH0COMFEN Channel 0 output compare fast enable When this bit is set the effect of an event on the trigger in i...

Page 389: ...0 input signal according to fSAMP and record the number of times of the same level of the signal After reaching the filtering capacity configured by this bit it is considered to be an effective level The filtering capability configuration is as follows CH0CAPFLT 3 0 Times fSAMP 4 b0000 Filter disabled 4 b0001 2 fCK_TIMER 4 b0010 4 4 b0011 8 4 b0100 6 fDTS 2 4 b0101 8 4 b0110 6 fDTS 4 4 b0111 8 4 b...

Page 390: ...ure compare function enable Refer to CH1EN description 3 2 Reserved Must be kept at reset value 1 CH0P Channel 0 capture compare function polarity When channel 0 is configured in output mode this bit specifies the output signal polarity 0 Channel 0 high level is active level 1 Channel 0 low level is active level When channel 0 is configured in input mode this bit specifies the IS0signal polarity 0...

Page 391: ...ounter value Writing to this bit filed can change the value of the counter Prescaler register TIMERx_PSC Address offset 0x28 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 PSC 15 0 Prescaler valu...

Page 392: ...h as 0xFFFF which is larger than user expected value Channel 0 capture compare value register TIMERx_CH0CV Address offset 0x34 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH0VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH0VAL 15 0 Captur...

Page 393: ...3 2 1 0 CH1VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH1VAL 15 0 Capture or compare value of channel1 When channel 1 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 1 is configured in output mode this bit filed contains value to be compared to the c...

Page 394: ...her Timers The general level2 timer module Timer9 10 12 13 is available only in the GD32F10x_XD devices 15 4 2 Characteristics Total channel num 1 Counter width 16bit Source of count clock is selectable internal clock internal trigger external input external trigger Multiple counter modes count up count down count up down Programmable prescaler 16 bit Factor can be changed on the go Each channel i...

Page 395: ...nitialization software output mask and polarity control CH0_O TIMERx_TRGO Interrupt Update Cap Com PSC TIMER_CK PSC_CLK 15 4 4 Function overview Clock source configuration The general level2 TIMER can only being clocked by the CK_TIMER Internal timer clock CK_TIMER which is from module RCU The general level2 TIMER has only one clock source which is the internal CK_TIMER used to drive the counter p...

Page 396: ...nter clock PSC_CK is obtained by the TIMER_CK through the prescaler and the prescale factor can be configured from 1 to 65536 through the prescaler register TIMERx_PSC The new written prescaler value will not take effect until the next update event Figure 15 66 Timing chart of PSC value change from 0 to 2 TIMER_CK CEN PSC_CLK CNT_REG Reload Pulse Prescaler CNT Prescaler shadow 94 95 96 97 98 99 0 ...

Page 397: ...value will be initialized to 0 and generates an update event If the UPDIS bit in TIMERx_CTL0 register is set the update event is disabled When an update event occurs all the shadow registers counter auto reload register prescaler register are updated Figure 15 67 Up counter timechart PSC 0 2 and Figure 15 68 Up counter timechart change TIMERx_CAR on the go show some examples of the counter behavio...

Page 398: ...ter to 0 in a count down direction Once the counter reaches to 0 the counter will start counting down from the counter reload value again The update event is generated each time when underflows The counting direction bit DIR in the TIMERx_CTL0 register should be set to 1 for the down counting mode When the update event is set by the UPG bit in the TIMERx_SWEVG register the counter value will be in...

Page 399: ...gure 15 69 Down counter timechart PSC 0 2 CEN PSC_CLK CNT_REG 5 4 3 2 1 0 99 98 97 96 95 94 93 92 Update event UPE Update interrupt flag UPIF CNT_REG 3 Update event UPE Update interrupt flag UPIF Hardware set Software clear Hardware set PSC 0 PSC 2 TIMER_CK 91 PSC_CLK 2 1 0 99 98 ...

Page 400: ...d value subtract 1 in the up counting direction and generates an underflow event when the counter counts to 1 in the down counting direction The counting direction bit DIR in the TIMERx_CTL0 register is read only and indicates the counting direction when in the center aligned mode Setting the UPG bit in the TIMERx_SWEVG register will initialize the counter value to 0 and generates an update event ...

Page 401: ...ture and output compare channels The general level2 timer has one independent channel which can be used as capture inputs or compare match outputs Each channel is built around a channel capture compare register including an input stage channel controller and an output stage Channel input capture function Channel input capture function allows the channel to perform measurements such as pulse timing...

Page 402: ...re detected You can select one of them by CHxP One more selector is for the other channel and trig controlled by CHxMS The IC_prescaler make several the input event generate one effective capture event On the capture event CHxVAL will restore the value of Counter So the process can be divided to several steps as below Step1 Filter configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the input signal ...

Page 403: ...omparator Compare output control CHxCOMCTL Output enable and polarity selector CHxP CHxE OxCPRE CHx_O CNT CHxCV CNT CHxCV CNT CHxCV Figure 15 73 Channel output compare principle x 0 shows the principle circuit of channels output compare function The relationship between the channel output signal CHx_O and the OxCPRE signal more details refer to Channel output prepare signal is described as blew Th...

Page 404: ... timechart below show the three compare modes toggle set clear CAR 0x63 CHxVAL 0x3 Figure 15 74 Output compare under three modes CEN CNT_REG 00 01 02 03 04 05 62 63 Overflow match toggle CNT_CLK OxCPRE 00 01 02 03 04 05 62 63 01 02 03 04 05 00 match set match clear OxCPRE OxCPRE Channel output prepare signal When the TIMERx is used in the compare match output mode the OxCPRE signal Channel x Outpu...

Page 405: ...special function of the OxCPRE signal is a forced output which can be achieved by setting the CHxCOMCTL field to 0x04 0x05 Here the output can be forced to an inactive active level irrespective of the comparison condition between the counter and the TIMERx_CHxCV values The OxCPRE signal can be forced to 0 when the ETIFP signal is derived from the external ETI pin and when it is set to a high level...

Page 406: ... to specify division factor between the CK_TIMER and the dead time and digital filter sample clock DTS 00 fDTS fCK_TIMER 01 fDTS fCK_TIMER 2 10 fDTS fCK_TIMER 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter aligns mode selection 00 No center aligned mode edge aligne...

Page 407: ...underflow event The restart mode generates an update event 1 This event generates update interrupts or DMA requests The counter generates an overflow or underflow event 1 UPDIS Update disable This bit is used to enable or disable the update event generation 0 Update event enable When an update event occurs the corresponding shadow registers are loaded with their preloaded values These events gener...

Page 408: ...MERx_SWEVG register is set 001 Enable When a conter start event occurs a TRGO trigger signal is output The counter start source CEN control bit is set The trigger input in pause mode is high 010 When an update event occurs a TRGO trigger signal is output The update source depends on UPDIS bit and UPS bit 011 When a capture or compare pulse event occurs in channel0 a TRGO trigger signal is output 1...

Page 409: ... Reserved CH0IF UPIF rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31 10 Reserved Must be kept at reset value 9 CH0OF Channel 0 over capture flag When channel 0 is configured in input mode this flag is set by hardware when a capture event occurs while CH0IF flag has already been set This flag is cleared by software 0 No over capture interrupt occurred 1 Over capture interrupt occurred 8 2 Reserved Mu...

Page 410: ...generate a capture or compare event in channel 0 it is automatically cleared by hardware When this bit is set the CH1IF flag is set the corresponding interrupt or DMA request is sent if enabled In addition if channel 1 is configured in input mode the current value of the counter is captured in TIMERx_CH0CV register and the CH0OF flag is set if the CH0IF flag was already high 0 No generate a channe...

Page 411: ...re register TIMERx_CH0CV 011 Toggle on match O0CPRE toggles when the counter is equals to the output compare register TIMERx_CH0CV 100 Force low O0CPRE is forced to low level 101 Force high O0CPRE is forced to high level 110 PWM mode0 When counting up O0CPRE is high when the counter is smaller than TIMERx_CH0CV and low otherwise When counting down O0CPRE is low when the counter is larger than TIME...

Page 412: ...ster is reset 00 Channel 0 is programmed as output mode 01 Channel 0 is programmed as input mode IS0 is connected to CI0FE0 10 Reserved 11 Reserved Input capture mode Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 4 CH0CAPFLT 3 0 Channel 0 input capture filter control The CI0 input signal can be filtered by digital filter and this bit field configure the filtering capability ...

Page 413: ...rd 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH0P CH0EN rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 CH0P Channel 0 capture compare polarity When channel 0 is configured in output mode this bit specifies the output signal polarity 0 Channel 0 high level is active level 1 Channel 0 low level is active...

Page 414: ...ed indicates the current counter value Writing to this bit filed can change the value of the counter Prescaler register TIMERx_PSC Address offset 0x28 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15...

Page 415: ...h as 0xFFFF which is larger than user expected value Channel 0 capture compare value register TIMERx_CH0CV Address offset 0x34 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH0VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH0VAL 15 0 Captur...

Page 416: ...GD32F10x User Manual 416 shadow register updates every update event ...

Page 417: ...o Single pulse mode is supported Auto reload function Interrupt output or DMA request on update event 15 5 3 Block diagram Figure 15 75 Basic timer block diagram provides details on the internal configuration of the basic timer Figure 15 75 Basic timer block diagram PSC Trigger processor Trigger Selector Counter Counter Register Interrupt Register set and update Interrupt collector APB BUS CK_TIME...

Page 418: ...of internal clock divided by 1 CK_TIMER CEN PSC_CLK TIMER_CK CNT_REG Reload Pulse 17 18 19 20 21 22 update event generate UPG 23 00 01 02 03 04 05 06 07 Update event UPE Clock prescaler The counter clock PSC_CK is obtained by the TIMER_CK through the prescaler and the prescale factor can be configured from 1 to 65536 through the prescaler register TIMERx_PSC The new written prescaler value will no...

Page 419: ... will start counting up from 0 again The update event is generated at each counter overflow When the update event is set by the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event If set the UPDIS bit in TIMERx_CTL0 register the update event is disabled When an update event occurs all the shadow registers counter auto reload register presca...

Page 420: ...K 8 PSC_CLK 97 98 99 0 1 Figure 15 79 Timing chart of up counting mode change TIMERx_CAR ongoing TIMER_CK CEN PSC_CLK CNT_REG 94 95 96 97 98 99 0 1 2 3 4 5 6 7 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule CNT_REG 113 114 115 116 117 118 119 120 0 1 2 98 99 0 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule 120 99 A...

Page 421: ...the single pulse mode it is necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter then the CEN bit keeps at a high state until the update event occurs or the CEN bit is written to 0 by software If the CEN bit is cleared to 0 using software the counter will be stopped and its value held Timer debug mode When the Cortex M3 halted and the TIMERx_HOLD configu...

Page 422: ...served Must be kept at reset value 3 SPM Single pulse mode 0 Single pulse mode disable Counter continues after update event 1 Single pulse mode enable The counter counts until the next update event occurs 2 UPS Update source This bit is used to select the update event sources by software 0 These events generate update interrupts or DMA requests The UPG bit is set The counter generates an overflow ...

Page 423: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MMC 2 0 Reserved rw Bits Fields Descriptions 31 7 Reserved Must be kept at reset value 6 4 MMC 2 0 Master mode control These bits control the selection of TRGO signal which is sent in master mode to slave timers for synchronization function 000 When a counter reset event occurs a TGRO trigger sig...

Page 424: ... rw Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 UPDEN Update DMA request enable 0 disabled 1 enabled 7 1 Reserved Must be kept at reset value 0 UPIE Update interrupt enable 0 disabled 1 enabled Interrupt flag register TIMERx_INTF Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reser...

Page 425: ... 1 Reserved Must be kept at reset value 0 UPG This bit can be set by software and cleared by hardware automatically When this bit is set the counter is cleared The prescaler counter is cleared at the same time 0 No generate an update event 1 Generate an update event Counter register TIMERx_CNT Address offset 0x24 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 2...

Page 426: ...The value of this bit filed will be loaded to the corresponding shadow register at every update event Counter auto reload register TIMERx_CAR Address offset 0x2C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CARL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at re...

Page 427: ...GD32F10x User Manual 427 value ...

Page 428: ...supports multiprocessor communication mode and hardware flow control protocol CTS RTS The USART supports DMA function for high speed data communication except UART4 16 2 Characteristics NRZ standard format Asynchronous full duplex communication Programmable baud rate generator Divided from the peripheral clocks PCLK2 for USART0 PCLK1 for USART1 2 and UART3 4 Oversampling by 16 Maximum speed up to ...

Page 429: ...urs at these events when the corresponding interrupt enable bits are set While USART0 1 2 is fully implemented UART3 4 is only partially implemented with the following features not supported Smartcard mode Synchronous mode Hardware flow control protocol CTS RTS 16 3 Function overview The interface is externally connected to another device by the main pins listed as following Table 16 1 USART impor...

Page 430: ...ata frame is configured by the WL bit in the USART_CTL0 register The last data bit can be used as parity check bit by setting the PCEN bit in USART_CTL0 register When the WL bit is reset the parity bit is the 7th bit When the WL bit is set the parity bit is the 8th bit The method of calculating the parity bit is selected by the PM bit in USART_CTL0 register Figure 16 2 USART character frame 8 bits...

Page 431: ...DIV UCLK 16 Baud Rate 16 1 For example when oversampled by 16 1 Get USARTDIV by caculating the value of USART_BUAD If USART_BUAD 0x21D then INTDIV 33 0x21 FRADIV 13 0xD USARTDIV 33 13 16 33 81 2 Get the value of USART_BUAD by calculating the value of USARTDIV If USARTDIV 30 37 then INTDIV 30 0x1E 16 0 37 5 92 the nearest integer is 6 so FRADIV 6 0x6 USART_BUAD 0x1E6 Note If the roundness of FRADIV...

Page 432: ... DENT bit in USART_CTL2 if multibuffer communication is selected 5 Set the baud rate in USART_BAUD 6 Set the TEN bit in USART_CTL0 7 Wait for the TBE being asserted 8 Write the data to in the USART_DATA register 9 Repeat step7 8 for each data if DMA is not enabled 10 Wait until TC 1 to finish Figure 16 3 USART transmit procedure Write data0 to USART_DATA by DMA or software set by hardware Write da...

Page 433: ...f a frame bit is 0 the frame bit is confirmed as a 0 else 1 If the three samples of any bit of a frame are not the same whatever it is a start bit data bit parity bit or stop bit a noisy error NERR status will be generated for the frame An interrupt is generated if the receive DMA is enabled and the ERRIE bit in USART_CTL2 register is set Figure 16 4 Oversampling method of a receive frame bit 0 2 ...

Page 434: ... buffer The DENT bit in USART_CTL2 is used to enable the DMA transmission and the DENR bit in USART_CTL2 is used to enable the DMA reception When DMA is used for USART transmission DMA transfers data from internal SRAM to the transmit data buffer of the USART The configuration step is shown in Figure 16 5 Configuration step when using DMA for USART transmission Figure 16 5 Configuration step when ...

Page 435: ...ration step when using DMA for USART reception Set the address of USART_DATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA interrupt enable priority etc Enable the DMA channel for USART When the number of the data received by USART reaches the DMA transfer num...

Page 436: ...e USART transmitter monitors the nCTS input pin to decide if a data frame can be transmitted If the TBE bit in USART_STAT is 0 and the nCTS signal is low the transmitter transmits the data frame When the nCTS signal goes high during a transmission the transmitter stops after the current transmission is accomplished Figure 16 8 Hardware flow control nCTS RX nRTS RTS flow control CTS flow control TX...

Page 437: ...ART The status bits are available in the USART_STAT register If the LSB 4 bits of an address frame differ from the ADDR 3 0 bits in the USART_CTL1 register the hardware sets the RWU bit and enters mute mode automatically In this situation the RBNE bit is not set If the address match method is selected the receiver does not check the parity value of an address frame by default If the PCEN bit in US...

Page 438: ...T_CTL1 The LMEN bit in USART_CTL1 and SCEN HDEN IREN bits in USART_CTL2 should be reset in synchronous mode The CK pin is the synchronous USART transmitter clock output and can be only activated when the TEN bit is enabled No clock pulse will be sent through the CK pin during the start bit and stop bit transmission The CLEN bit in USART_CTL1 can be used to determine whether the clock is output or ...

Page 439: ...t6 bit7 bit0 bit1 bit2 bit3 CK pin CPL 0 CPH 0 16 3 10 IrDA SIR ENDEC mode The IrDA mode is enabled by setting the IREN bit in USART_CTL2 The LMEN STB 1 0 CKEN bits in USART_CTL1 and HDEN SCEN bits in USART_CTL2 should be reset in IrDA mode In IrDA mode the USART transmission data frame is modulated in the SIR transmit encoder and transmitted to the infrared LED through the TX pin The SIR receive ...

Page 440: ... PSC clock While it can detect a pulse by chance if the pulse width is greater than 1 but smaller than 2 times PSC clock Because the IrDA is a half duplex protocol the transmission and the reception should not be carried out at the same time in the IrDA SIR ENDEC block Figure 16 14 IrDA data modulation Normal tx frame Stop Start 1 0 0 0 0 0 0 1 1 1 1 Stop Start 1 0 1 1 1 1 0 0 0 0 0 TX pin Normal ...

Page 441: ...vide ratio is configured by the PSC 4 0 bits in USART_GP register The CK pin only provides a clock source to the smart card The smartcard mode is a half duplex communication protocol When connected to a smartcard the TX pin must be configured as open drain and an external pull up resistor will be needed which drives a bidirectional line that is also driven by the smartcard The data frame consists ...

Page 442: ...end the data The NACK signal is enabled by setting the NKEN bit in USART_CTL2 The idle frame and break frame are not applied for the smartcard mode 16 3 13 USART interrupts The USART interrupt events and flags are listed in the table below Table 16 3 USART interrupt requests Interrupt event Event flag Control register Enable Control bit Transmit data buffer empty TBE USART_CTL0 TBEIE CTS toggled f...

Page 443: ...GD32F10x User Manual 443 Figure 16 16 USART interrupt mapping diagram ORERR RBNEIE PERR PEIE LBDF LBDIE FERR NERR ORERR ERRIE OR TCIE TBEIE CTSF CTSIE USART_INT TC TBE RBNE RBNEIE IDLEF IDLEIE ...

Page 444: ...set by hardware when the nCTS input toggles An interrupt occurs if the CTSIE bit in USART_CTL2 is set Software can clear this bit by writing 0 to it 0 The status of the nCTS line does not change 1 The status of the nCTS line has changed This bit is not available for UART3 4 8 LBDF LIN break detected flag If LMEN bit in USART_CTL1 is set this bit is set by hardware when LIN break is detected An int...

Page 445: ...ected in idle state for a frame time An interrupt occurs if the IDLEIE bit in USART_CTL0 is set Software can clear this bit by reading the USART_STAT and USART_DATA registers one by one 0 The USART module does not detect an IDLE frame 1 The USART module has detected an IDLE frame 3 ORERR Overrun error This bit is set if the RBNE is not cleared and a new data frame is received through the receive s...

Page 446: ...ity error 16 4 2 Data register USART_DATA Offset 0x04 Reset value Undefined This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DATA 8 0 rw Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 0 DATA 8 0 Transmit or read data value Software can write these bits to update the transmit...

Page 447: ...gister has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UEN WL WM PCEN PM PERRIE TBEIE TCIE RBNEIE IDLEIE TEN REN RWU SBKCMD rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 14 Reserved Must be kept at reset value 13 UEN USART enable 0 USART disabled 1 USART enabled 12 WL Word length 0 8 D...

Page 448: ...pt occurs when the RBNE bit or the ORERR bit in USART_STAT is set 0 Read data register not empty interrupt and overrun error interrupt disabled 1 Read data register not empty interrupt and overrun error interrupt enabled 4 IDLEIE IDLE line detected interrupt enable If this bit is set an interrupt occurs when the IDLEF bit in USART_STAT is set 0 IDLE line detected interrupt disabled 1 IDLE line det...

Page 449: ...ved ADDR 3 0 rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 15 Reserved Must be kept at reset value 14 LMEN LIN mode enable 0 LIN mode disabled 1 LIN mode enabled This bit field cannot be written when the USART is enabled UEN 1 13 12 STB 1 0 STOP bits length 00 1 Stop bit 01 0 5 Stop bit 10 2 Stop bits 11 1 5 Stop bit This bit field cannot be written when the USART is enabled UEN 1 Only 1 ...

Page 450: ...itten when the USART is enabled UEN 1 This bit is reserved for UART3 4 7 Reserved Must be kept at reset value 6 LBDIE LIN break detected interrupt enable If this bit is set an interrupt occurs when the LBDF bit in USART_STAT is set 0 LIN break detected interrupt is disabled 1 LIN break detected interrupt is enabled 5 LBLEN LIN break frame length This bit specifies the length of a LIN break frame 0...

Page 451: ... UART3 4 8 RTSEN RTS enable This bit enables the RTS hardware flow control function 0 RTS hardware flow control disabled 1 RTS hardware flow control enabled This bit field cannot be written when the USART is enabled UEN 1 This bit is reserved for UART3 4 7 DENT DMA request enable for transmission 0 DMA request is disabled for transmission 1 DMA request is enabled for transmission 6 DENR DMA reques...

Page 452: ...of USART 0 IrDA disabled 1 IrDA enabled This bit field cannot be written when the USART is enabled UEN 1 This bit is reserved in USART1 0 ERRIE Error interrupt enable When DMA request for reception is enabled DENR 1 if this bit is set an interrupt occurs when any one of the FERR ORERR and NERR bits in USART_STAT is set 0 Error interrupt disabled 1 Error interrupt enabled 16 4 7 Guard time and pres...

Page 453: ...cy 00000000 Reserved never program this value 00000001 divides by 1 00000010 divides by 2 11111111 divides by 255 When the USART works in IrDA normal mode these bits must be set to 00000001 When the USART smartcard mode is enabled the PSC 4 0 bits specify the division factor that is used to divide the peripheral clock APB1 APB2 to generate the smartcard clock CK The actual division factor is twice...

Page 454: ...2C interface provides DMA mode for users to reduce CPU overload 17 2 Characteristics Parallel bus to I2C bus protocol conversion and interface Both master and slave functions with the same interface Bi directional data transfer between master and slave Supports 7 bit and 10 bit addressing and General Call Addressing Multi master capability Supports standard mode up to 100 kHz fast mode up to 400 k...

Page 455: ...clock signals and terminates a transfer Slave The device addressed by a master Multi master More than one master can attempt to control the bus at the same time without corrupting the message Synchronization Procedure to synchronize the clock signals of two or more devices Arbitration Procedure to ensure that if more than one master tries to control the bus simultaneously only one is allowed to do...

Page 456: ...pend on the associated level of VDD 17 3 2 Data validation The data on the SDA line must be stable during the HIGH period of the clock The HIGH or LOW state of the SDA line can only change when the clock signal on the SCL line is LOW see Figure 17 2 Data validation One clock pulse is generated for each data bit transferred Figure 17 2 Data validation SDA SCL 17 3 3 START and STOP signal All transm...

Page 457: ...e master with the longest LOW period Masters with shorter LOW period enter a HIGH wait state during this time Figure 17 4 Clock synchronization CLK1 CLK2 SCL 17 3 5 Arbitration Arbitration like synchronization is part of the protocol where more than one master is used in the system Slaves are not involved in the arbitration procedure A master may start a transfer only if the bus is free Two master...

Page 458: ...re the I2C slave always responds to a General Call Address 0x00 The I2C block supports both 7 bit and 10 bit address modes An I2C master always initiates or ends a transfer using START or STOP signal and it s also responsible for SCL clock generation Figure 17 6 I2C communication flow with 7 bit address Start Slave address W 0 ACK DATA0 ACK DATAN ACK Stop data transfer N 1 bytes From master to sla...

Page 459: ...ed registers in I2C_CTL1 to make sure correct I2C timing After enabled and configured I2C operates in its default slave state and waits for START signal followed by address on I2C bus 2 After receiving a START signal followed by a matched address either in 7 bit format or in 10 bit format the I2C hardware sets the ADDSEND bit in I2C_STAT0 register which should be monitored by software either by po...

Page 460: ...ftware that the transmission completes Software clears AERR bit by writing 0 to it Figure 17 9 Programming model for slave transmitting mode 10 bit address mode IDLE Master generates START condition Master sends Address Slave sends Acknowledge Master generates repeated START condition Master sends header Slave sends Acknowledge SCL stretched by slave Slave sends DATA 1 Master sends Acknowledge Dat...

Page 461: ...llowed by a matched 7 bit or 10 bit address the I2C hardware sets the ADDSEND bit in I2C status register 0 which should be monitored by software either by polling or interrupt After that software should read I2C_STAT0 and then I2C_STAT1 to clear ADDSEND bit The I2C begins to receive data on I2C bus as soon as ADDSEND bit is cleared 3 As soon as the first byte is received RBNE is set by hardware So...

Page 462: ...ble I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing After enabled and configured I2C operates in its default slave state and waits for START signal followed by address on I2C bus 2 Software sets START bit requesting I2C to generate a START signal on I2C bus 3 After sending a START signal the I2C hardware sets the SBSEND bit in I2C_STAT0...

Page 463: ...can write the second byte to I2C_DATA and this time TBE is cleared because neither I2C_DATA nor shift register is empty 7 Any time TBE is set software can write a byte to I2C_DATA as long as there is still data to be transmitted 8 During the transmission of the second last byte software writes the last data to I2C_DATA to clear the TBE flag and doesn t care TBE anymore So TBE will be asserted afte...

Page 464: ...ion Software Flow 2 Set START Set SBSEND SCL stretched by master 3 Clear SBSEND SCL stretched by master SCL stretched by master Programming model in master receiving mode In master receiving mode a master is responsible for generating NACK for the last byte reception and then sending STOP a condition on I2C bus So special attention should be paid to ensure the correct ending of data reception Two ...

Page 465: ... sent out Software should clear the SBSEND bit by reading I2C_STAT0 and writing header to I2C_DATA Then the header is sent out to I2C bus and ADDSEND is set again Software should again clear ADDSEND by reading I2C_STAT0 and then I2C_STAT1 5 As soon as the first byte is received RBNE is set by hardware Software now can read the first byte from I2C_DATA and RBNE is cleared as well 6 Any time RBNE is...

Page 466: ... condition Set SBSEND 4 Clear SBSEND SCL stretched by master Master sends Header Slave sends Acknowledge Set ADDSEND 4 Clear ADDSEND SCL stretched by master 6 Read DATA N 1 7 Clear ACKEN Set STOP Solution B 1 First of all enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing After enabled and configured I2C operates in its default slav...

Page 467: ... using solution B 10 bit address mode the N 2 byte is not read out by software so after the N 1 byte is received both BTC and RBNE are asserted The bus is stretched by master to prevent the reception of the last byte Then software should clear ACKEN bit 7 Software reads out N 2 byte clearing BTC After this the N 1 byte is moved from shift register to I2C_DATA and bus is released and begins to rece...

Page 468: ... RBNE 8 Read DATA N 2 I2C Line State Hardware Action Software Flow 2 Set START Set SBSEND SCL stretched by master 3 Clear SBSEND SCL stretched by master 4 Set START Master generates repeated START condition Set SBSEND 4 Clear SBSEND SCL stretched by master Master sends Header Slave sends Acknowledge Set ADDSEND 4 Clear ADDSEND SCL stretched by master 7 Clear ACKEN Slave sends DATA N 2 Master sends...

Page 469: ...r to the specification of the DMA controller for the configuration method of a DMA stream The DMA controller must be configured and enabled before the I2C transfer When the configured number of bytes have been transferred the DMA controller generates End of Transfer EOT interrupt DMA will send an End of Transmission EOT signal to the I2C interface and generates a DMA full transfer finish interrupt...

Page 470: ... Dynamic reconfiguration of the hardware and software allows bus devices to be hot plugged and used immediately without restarting the system The devices are recognized automatically and assigned unique addresses This advantage results in a plug and play user interface In this protocol there is a very useful distinction between a system host and all the other devices in the system that is the host...

Page 471: ...its should be configured to desired values 2 In order to support address resolution protocol ARP ARPEN 1 the software should respond to HSTSMB flag in SMBus Host Mode SMBSEL 1 or DEFSMB flag in SMBus Device Mode and implement the function of ARP protocol 3 In order to support SMBus Alert Mode the software should respond to SMBALT flag and implement the related function 17 3 12 Status errors and in...

Page 472: ...GD32F10x User Manual 472 Error Name Description AERR No acknowledge received PECERR CRC value doesn t match SMBTO Bus timeout in SMBus mode SMBALT SMBus Alert ...

Page 473: ...ld wait until the I2C lines are released to reset the I2C 0 I2C is not reset 1 I2C is reset 14 Reserved Must be kept at reset value 13 SALT SMBus Alert Issue alert through SMBA pin Software can set and clear this bit and hardware can clear this bit 0 Don t issue alert through SMBA pin 1 Issue alert through SMBA pin 12 PECTRANS PEC transfer Software sets and clears this bit while hardware clears th...

Page 474: ... START condition on I2C bus This bit is set and cleared by software and cleared by hardware when a START condition is detected or I2CEN 0 0 START will not be sent 1 START will be sent 7 DISSTRC SCL stretching Whether to stretch SCL low when data is not ready in slave mode This bit is set and cleared by software 0 SCL stretching is enabled 1 SCL stretching is disabled 6 GCEN Whether or not to respo...

Page 475: ...ext DMA EOT is not the last transfer 1 Next DMA EOT is the last transfer 11 DMAON DMA is mode switched on 0 DMA mode is switched off 1 DMA mode is switched on 10 BUFIE 0 Buffer interrupt is disabled 1 Buffer interrupt is enabled which means that interrupt will be generated when TBE 1 or RBNE 1 if EVIE 1 9 EVIE Event interrupt enable 0 Event interrupt is disabled 1 Event interrupt is enabled which ...

Page 476: ...00 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDFOR MAT Reserved ADDRESS 9 8 ADDRESS 7 1 ADDRES S0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 ADDFORMAT Address format for the I2C slave 0 7 bit address 1 10 bit address 14 10 Reserved Must...

Page 477: ...buffer register I2C_DATA Address offset 0x10 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRB 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 TRB 7 0 Transmission or reception data buffer 17 4 6 Transfer status register 0 ...

Page 478: ...lculated PEC 1 Received PEC doesn t match the calculated PEC I2C will send NACK careless of ACKEN bit 11 OUERR Over run or under run situation occurs in slave mode when SCL stretching is disabled In slave receiving mode if the last byte in I2C_DATA is not read out while the following byte is already received over run occurs In slave transmitting mode if the current byte is already sent out while t...

Page 479: ...2C_STAT0 and then writing I2C_CTL0 0 STOP signal not detected in slave mode 1 STOP signal detected in slave mode 3 ADD10SEND Header of 10 bit address is sent in master mode This bit is set by hardware and cleared by reading I2C_STAT0 and writing I2C_DATA 0 No header of 10 bit address is sent in master mode 1 Header of 10 bit address is sent in master mode 2 BTC Byte transmission is completed If a ...

Page 480: ...erved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PECV 7 0 DUMODF HSTSMB DEFSMB RXGC Reserved TR I2CBSY MASTER r r r r r r r r Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 8 PECV 7 0 Packet Error Checking value that calculated by hardware when PEC is enabled 7 DUMODF Dual flag in slave mode indicates which address matches with the address in Dual Address mode This bit is cleare...

Page 481: ...munication 1 I2C communication active 0 MASTER A flag indicating whether I2C block is in master or slave mode This bit is set by hardware when a START signal generates This bit is cleared by hardware after a STOP signal or I2CEN 0 or LOSTARB 1 0 Slave mode 1 Master mode 17 4 8 Clock configure register I2C_CKCFG Address offset 0x1C Reset value 0x0000 0000 This register can be accessed by half word ...

Page 482: ...ple of 3 the baud rate will be more accurate If DTCY is 1 when PCLK1 is an integral multiple of 25 the baud rate will be more accurate 17 4 9 Rise time register I2C_RT Address offset 0x20 Reset value 0x0000 0002 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RISETIME 5 0 rw Bit...

Page 483: ... 2 Characteristics 18 2 1 SPI characteristics Master or slave operation with full duplex or half duplex or simplex mode Separate transmit and receive buffer 16 bits wide Data frame size can be 8 or 16 bits Bit order can be LSB or MSB Software and hardware NSS management Hardware CRC calculation transmission and checking Transmission and reception using DMA 18 2 2 I2S characteristics Master or slav...

Page 484: ... I O Master SPI clock output Slave SPI clock input MISO I O Master data reception line Slave data transmission line Master with bidirectional mode not used Slave with bidirectional mode data transmission and reception line MOSI I O Master data transmission line Slave data reception line Master with bidirectional mode data transmission and reception line Slave with bidirectional mode not used NSS I...

Page 485: ...K CKPH 0 CKPL 0 SCK CKPH 0 CKPL 1 SCK CKPH 1 CKPL 0 SCK CKPH 1 CKPL 1 LF 1 FF16 0 MOSI MISO NSS D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 sample D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 In normal mode the length of data is configured by the FF16 bit in the SPI_CTL0 register Data length is 16 bits if FF16 1 otherwise is 8 bits Data order is configured by LF bit in SPI_CTL0 register and SPI will first send the LSB if ...

Page 486: ...S goes low after SPI is enabled The application may also use a general purpose IO as NSS pin to realize more flexible NSS Table 18 3 NSS function in master mode Mode Register configuration Description Master hardware NSS output mode MSTMOD 1 SWNSSEN 0 NSSDRV 1 Applicable to single master mode The master uses the NSS pin to control the SPI slave device At this time the NSS is configured as the hard...

Page 487: ...O 1 BDEN 0 BDOEN Don t care MOSI not used MISO reception MTB Master transmission with bidirectional connection MSTMOD 1 RO 0 BDEN 1 BDOEN 1 MOSI transmission MISO not used MRB Master reception with bidirectional connection MSTMOD 1 RO 0 BDEN 1 BDOEN 0 MOSI reception MISO not used SFD Slave full duplex MSTMOD 0 RO 0 BDEN 0 BDOEN Don t care MOSI reception MISO transmission STU Slave transmission wit...

Page 488: ... used MISO reception Figure 18 3 A typical full duplex connection Master MFD MISO MOSI SCK NSS Slave SFD MISO MOSI SCK NSS Figure 18 4 A typical simplex connection Master receive Slave transmit Master MRU MISO MOSI SCK NSS Slave STU MISO MOSI SCK NSS Figure 18 5 A typical simplex connection Master transmit only Slave receive Master MTU MISO MOSI SCK NSS Slave SRU MISO MOSI SCK NSS ...

Page 489: ...depending on the operating modes described in SPI operation modes section 7 Enable the SPI set the SPIEN bit Note During communication CKPH CKPL MSTMOD PSC 2 0 and LF bits should not be changed Basic transmission and reception sequence Transmission sequence After the initialization sequence the SPI is enabled and stays at idle state In master mode the transmission starts when the application write...

Page 490: ... disabled then SPI enabled SPI operation sequence in different modes In full duplex mode either MFD or SFD the RBNE and TBE flags should be monitored and then follow the sequences described above The transmission mode MTU MTB STU or STB is similar to the transmission sequence of full duplex mode regardless of the RBNE and RXORERR bits The master reception mode MRU or MRB is different from the rece...

Page 491: ...nd read data from the SPI_DATA register automatically 18 3 7 CRC function There are two CRC calculators in SPI one for transmission and the other for reception The CRC calculation uses the polynomial defined in SPI_CRCPOLY register Application can enable the CRC function by setting CRCEN bit in SPI_CTL0 register The CRC calculators continuously calculate CRC for each bit transmitted and received o...

Page 492: ...ot controlled by software This flag doesn t generate any interrupt Note TRANS is set after the first bit is transmitted So TBE or RBNE must be judged as the communication finished instead of TRANS Error conditions Configuration fault error CONFERR CONFERR is an error flag in master mode In NSS hardware mode and the NSSDRV is not enabled the CONFERR is set when the NSS pin is pulled low In NSS soft...

Page 493: ...4 1 I2S block diagram Figure 18 7 Block diagram of I2S Clock Generator SPI_MOSI I2S_SD SPI_NSS I2S_WS SPI_SCK I2S_CK I2S_MCK Master Control Logic Slave Control Logic TX Buffer Shift Register RX Buffer Control Registers 16 bits I2SCLK 16 bits LSB MSB PAD PAD O I O I PAD O I PAD O I APB There are five sub modules to support I2S function including control registers clock generator master control logi...

Page 494: ...ngth are configured by the DTLEN bit and CHLEN bit in the SPI_I2SCTL register Since the channel length must be greater than or equal to the data length four packet types are available They are 16 bit data packed in 16 bit frame 16 bit data packed in 32 bit frame 24 bit data packed in 32 bit frame and 32 bit data packed in 32 bit frame The data buffer for transmission and reception is 16 bit wide I...

Page 495: ...B MSB LSB I2S_WS Figure 18 11 I2S Phillips standard timing diagram DTLEN 10 CHLEN 1 CKPL 1 I2S_CK I2S_SD 32 bit data frame 1 channel left frame 2 channel right MSB MSB LSB I2S_WS When the packet type is 32 bit data packed in 32 bit frame two write or read operations to or from the SPI_DATA register are needed to complete the transmission of a frame In transmission mode if a 32 bit data is going to...

Page 496: ...its are zeros Figure 18 14 I2S Phillips standard timing diagram DTLEN 00 CHLEN 1 CKPL 0 I2S_CK I2S_SD 16 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 16 bit 0 MSB Figure 18 15 I2S Phillips standard timing diagram DTLEN 00 CHLEN 1 CKPL 1 I2S_CK I2S_SD 16 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 16 bit 0 MSB When the packet type is 16 bit data packed i...

Page 497: ...LEN 1 CKPL 1 I2S_CK I2S_SD 32 bit data frame 1 channel left frame 2 channel right MSB MSB LSB I2S_WS Figure 18 20 MSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 0 I2S_CK I2S_SD 24 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 8 bit 0 MSB Figure 18 21 MSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 1 I2S_CK I2S_SD 24 bit data frame 1 channel left frame ...

Page 498: ...I2S_WS 24 bit data MSB LSB Figure 18 25 LSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 1 I2S_CK I2S_SD 8 bit 0 frame 1 channel left frame 2 channel right I2S_WS 24 bit data MSB LSB When the packet type is 24 bit data packed in 32 bit frame two write or read operations to or from the SPI_DATA register are needed to complete the transmission of a frame In transmission mode if a 24 bit d...

Page 499: ...nd the long frame synchronization mode are available and configurable using the PCMSMOD bit in the SPI_I2SCTL register The SPI_DATA register is handled in the exactly same way as that for I2S Phillips standard The timing diagrams for each configuration of the short frame synchronization mode are shown below Figure 18 28 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 0 ...

Page 500: ...PL 1 I2S_CK I2S_SD 24 bit data MSB I2S_WS MSB frame 1 frame 2 8 bit 0 Figure 18 34 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 0 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB frame 1 frame 2 16 bit 0 Figure 18 35 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 1 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB frame 1 frame 2 16 bit 0 Th...

Page 501: ...L 0 I2S_CK I2S_SD 32 bits MSB I2S_WS MSB LSB frame 1 frame 2 13 bits Figure 18 39 PCM standard long frame synchronization mode timing diagram DTLEN 10 CHLEN 1 CKPL 1 I2S_CK I2S_SD 32 bits MSB I2S_WS MSB LSB frame 1 frame 2 13 bits Figure 18 40 PCM standard long frame synchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 0 I2S_CK I2S_SD 24 bit data MSB I2S_WS MSB frame 1 frame 2 13 bits 8 bit 0...

Page 502: ...I2S_CK I2S_MCK MCKOEN The block diagram of I2S clock generator is shown as Figure 18 44 Block diagram of I2S clock generator The I2S interface clocks are configured by the DIV bits the OF bit the MCKOEN bit in the SPI_I2SPSC register and the CHLEN bit in the SPI_I2SCTL register The source of I2S clock can be either PLL2 CK_PLL2 2 or CK_SYS in order to get the maximum accuracy The I2S bitrate can b...

Page 503: ...ailable operation modes including master transmission mode master reception mode slave transmission mode and slave reception mode The direction of I2S interface signals for each operation mode is shown in the Table 18 8 Direction of I2S interface signals for each operation mode Table 18 8 Direction of I2S interface signals for each operation mode Operation mode I2S_MCK I2S_CK I2S_WS I2S_SD Master ...

Page 504: ...ect I2S standard Configure the I2SOPMOD 1 0 bits to select I2S operation mode Configure the DTLEN 1 0 bits and the CHLEN bit to select I2S data format Configure the TBEIE bit the RBNEIE bit the ERRIE bit to enable I2S interrupt optional Configure the DMATEN bit and the DMAREN bit to enable I2S DMA function optional Configure the I2SEN bit to enable I2S No I2S master transmission sequence The TBE f...

Page 505: ...I2S it is mandatory to clear the I2SEN bit after the TBE flag is high and the TRANS flag is low I2S master reception sequence The RBNE flag is used to control the reception sequence As is mentioned before the RBNE flag indicates the reception buffer is not empty and an interrupt will be generated if the RBNEIE bit in the SPI_CTL1 register is set The reception sequence begins immediately when the I...

Page 506: ...ternal master starts the communication The transmission sequence begins when the external master sends the clock and when the I2S_WS signal requests the transfer of data The data has to be written to the SPI_DATA register before the master initiates the communication Software should write the next audio data into SPI_DATA register before the current data finishes Otherwise transmission underrun er...

Page 507: ... TRANS and I2SCH The user can use them to fully monitor the state of the I2S bus Transmit buffer empty flag TBE This bit is set when the transmission buffer is empty the software can write the next data to the transmission buffer by writing the SPI_DATA register Receive buffer not empty flag RBNE This bit is set when reception buffer is not empty which means that one data is received and stored in...

Page 508: ...letely received When overrun occurs the data in reception buffer is not updated and the newly incoming data is lost I2S interrupt events and corresponding enabled bits are summed up in the Table 18 9 I2S interrupt Table 18 9 I2S interrupt Interrupt flag Description Clear method Interrupt enable bit TBE Transmit buffer empty Write SPI_DATA register TBEIE RBNE Receive buffer not empty Read SPI_DATA ...

Page 509: ...KPH rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 BDEN Bidirectional enable 0 2 line unidirectional transmit mode 1 1 line bidirectional transmit mode The data transfers between the MOSI pin of master and the MISO pin of slave 14 BDOEN Bidirectional transmit output enable When BDEN is set this bit determines the direction of transf...

Page 510: ...SS software mode The NSS level depends on SWNSS bit 8 SWNSS NSS pin selection in NSS software mode 0 NSS pin is pulled low 1 NSS pin is pulled high This bit has an effect only when the SWNSSEN bit is set This bit has no meaning in SPI TI mode 7 LF LSB mode 0 Transmit MSB 1 Transmit LSB 6 SPIEN SPI enable 0 Disable SPI peripheral 1 Enable SPI peripheral 5 3 PSC 2 0 Master clock prescaler selection ...

Page 511: ...smit buffer empty interrupt enable 0 Disable TBE interrupt 1 Enable TBE interrupt An interrupt is generated when the TBE bit is set 6 RBNEIE Receive buffer not empty interrupt enable 0 Disable RBNE interrupt 1 Enable RBNE interrupt An interrupt is generated when the RBNE bit is set 5 ERRIE Errors interrupt enable 0 Disable error interrupt 1 Enable error interrupt An interrupt is generated when the...

Page 512: ...t and cleared by hardware 6 RXORERR Reception overrun error bit 0 No reception overrun error occurs 1 Reception overrun error occurs This bit is set by hardware and cleared by a read operation on the SPI_DATA register followed by a read access to the SPI_STAT register 5 CONFERR SPI configuration error bit 0 No configuration fault occurs 1 Configuration fault occurred In master mode the NSS pin is ...

Page 513: ... is not empty 18 5 4 Data register SPI_DATA Address offset 0x0C Reset value 0x0000 0000 This register can be accessed by byte 8 bit or half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPI_DATA 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 SPI_DATA 15 0 Data transfer register The hardwar...

Page 514: ...This register can be accessed by byte 8 bit or half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCRC 15 0 r Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 RCRC 15 0 RX CRC value When the CRCEN bit of SPI_CTL0 is set the hardware computes the CRC value of the received bytes and saves them in RCRC...

Page 515: ...ion is based on CRC8 standard and saves the value in TCR 7 0 when the Data frame format is set to 16 bit data CRC calculation is based on CRC16 standard and saves the value in TCRC 15 0 The hardware computes the CRC value after each transmitted bit when the TRANS is set a read to this register could return an intermediate value The different frame format LF bit of the SPI_CTL0 will get different C...

Page 516: ...M frame synchronization mode 0 Short frame synchronization 1 long frame synchronization This bit has a meaning only when PCM standard is used This bit should be configured when I2S mode is disabled This bit is not used in SPI mode 6 Reserved Must be kept at reset value 5 4 I2SSTD 1 0 I2S standard selection 00 I2S Phillips standard 01 MSB justified standard 10 LSB justified standard 11 PCM standard...

Page 517: ...rd 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MCKOEN OF DIV 7 0 rw rw rw Bits Fields Descriptions 31 10 Reserved Must be kept at reset value 9 MCKOEN I2S_MCK output enable 0 Disable I2S_MCK output 1 Enable I2S_MCK output This bit should be configured when I2S mode is disabled This bit is not used in SPI mode 8 OF Odd factor for th...

Page 518: ...GD32F10x User Manual 518 These bits are not used in SPI mode ...

Page 519: ...A system specifications are defined through the CE ATA workgroup website at www ce ata org 19 2 Characteristics The SDIO features include the following MMC Full support for Multimedia Card System Specification Version 4 2 and previous versions Card and three different data bus modes 1 bit default 4 bit and 8 bit SD Card Full support for SD Memory Card Specifications Version 2 0 SD I O Full support...

Page 520: ...ed synchronous to the host clock Two types of data transfer commands are defined Stream commands These commands initiate a continuous data stream they are terminated only when a stop command follows on the CMD line This mode reduces the command overhead to an absolute minimum only MMC supports Block oriented commands These commands send a data block successfully by CRC bits Both read and write ope...

Page 521: ...to Host Multiple block read operation Device to Host Device to Host Figure 19 3 SDIO multiple blocks write operation SDIO_CMD SDIO_DAT Block write operation Data stop operation Command Response Host to Device Device to Host Command Response Host to Device Device to Host DATA BLOCK CRC DATA BLOCK CRC Multiple block write operation Host to Device Host to Device Data transfers to from SD memory cards...

Page 522: ...transfer data unit which manage data transfer The AHB interface block contains access registers by AHB bus contains FIFO unit which is data FIFO used for data transfer and generates interrupt and DMA request signals Figure 19 6 SDIO block diagram SDIO controller HCLK 2 SDIOCLK SDIO_CMD SDIO_CLK SDIO_DAT 7 0 SDIO adapter control unit command unit data unit registers FIFO AHB interface interrupt DMA...

Page 523: ...fter entering to the 4 bit mode the card disconnects the internal pull ups of lines DAT1 and DAT2 DAT3 internal pull up is left connected due to the SPI mode CS usage Correspondingly right after entering to the 8 bit mode the card disconnects the internal pull ups of lines DAT1 DAT2 and DAT4 DAT7 Table 19 1 SDIO I O definitions Pin function Direction Description SDIO_CLK O SD SD I O MMC clock SDIO...

Page 524: ... response which have 48 bits or long response which have 136 bits The response stores in SDIO_RESP0 SDIO_RESP3 registers The command unit also generates the command status flags defined in SDIO_STAT register Command state machine CS_Idle After reset ready to send command 1 CSM enabled and WAITDEND enabled CS_Pend 2 CSM enabled and WAITDEND disabled CS_Send 3 CSM disabled CS_Idle Note The state mac...

Page 525: ...s when 4 bits data width BUSMODE bits in SDIO_CLKCTL register is 0b01 or SDIO_DAT 0 signal when 1 bit data width BUSMODE bits in SDIO_CLKCTL register is 0b00 The data transfer flow is controlled by Date State Machine DSM After a write operation to SDIO_DATACTL register and DATAEN in SDIO_DATACTL register is 1 the data transfer starts It sends data to card when DATADIR in SDIO_DATACTL register is 0...

Page 526: ...d DS_Idle 2 DSM disabled DS_Idle 3 Data timeout reached DS_Idle 4 Receives a start bit before timeout DS_Receive Note The command timeout programmed in the data timer register SDIO_DATATO DS_Receive Receive data from the card and write it to the data FIFO 1 Data block received DS_WaitR 2 Data transfer ended DS_WaitR 3 Data FIFO overrun error occurs DS_Idle 4 Data received and Read Wait Started and...

Page 527: ...n bytes BLKSZ in the SDIO_DATACTL register the host sends data in blocks of size BLKSZ each Program SDIO_CMDAGMT register with the data address where data should be written Program the SDIO command control register SDIO_CMDCTL CMDIDX with 24 CMDRESP with 1 SDIO card host waits for a short response CSMEN with 1 enable to send a command Other fields are their reset value When the CMDRECV flag is set...

Page 528: ... SD I O to get the content of this register CID register The Card Identification CID register is 128 bits wide It contains the card identification information used during the card identification phase Every individual Read Write RW card shall have a unique identification number The host can use CMD2 and CMD10 to get the content of this register CSD register The Card Specific Data register provides...

Page 529: ...ides information on the SD Memory Card s special features that were configured into the given card The size of SCR register is 64 bits This register shall be set in the factory by the SD Memory Card manufacturer The host can use ACMD51 to get the content of this register 19 5 2 Commands Commands types There are four kinds of commands defined to control the Card Broadcast commands bc no response Br...

Page 530: ...s CCC are coded as a parameter in the card specific data CSD register of each card providing the host with information on how to access the card For MMC cards Class 0 is mandatory and shall be supported The other classes are either mandatory only for specific card types or optional By using different classes several configurations can be chosen e g a block writable card or a stream readable card T...

Page 531: ...am read Block read Stream write Block write erase write protection Lock card application specific I O mode switch reserved CMD0 M CMD1 M CMD2 M CMD3 M CMD4 M CMD5 O CMD6 M CMD7 M CMD8 M CMD9 M CMD10 M CMD11 M CMD12 M CMD13 M CMD14 M CMD15 M CMD16 M CMD17 M CMD18 M CMD19 M CMD20 M CMD23 M CMD24 M CMD25 M CMD26 M CMD27 M CMD28 M CMD29 M CMD30 M CMD32 M CMD33 M ...

Page 532: ...D38 M CMD39 CMD40 CMD42 CMD50 O CMD52 O CMD53 O CMD55 M CMD56 M CMD57 O CMD60 M CMD61 M ACMD6 M ACMD13 M ACMD22 M ACMD23 M ACMD41 M ACMD42 M ACMD51 M Note 1 CMD1 CMD11 CMD14 CMD19 CMD20 CMD23 CMD26 CMD39 and CMD40 are only available for MMC CMD5 CMD32 34 CMD50 CMD52 CMD53 CMD57 and ACMDx are only available for SD card CMD60 CMD61 are only available for CE ATA device 2 All the ACMDs shall be preced...

Page 533: ...s connected to the host will respond CMD3 bcr 31 0 stuff bits R6 SEND_RELATIVE _ADDR Ask the card to publish a new relative address RCA CMD4 bc 31 16 DSR 15 0 stuff bits SET_DSR Programs the DSR of all cards CMD5 bcr 31 25 reserved bits 24 S18R 23 0 I O OCR R4 IO_SEND_OP_CO ND Only for I O cards It is similar to the operation of ACMD41 for SD memory cards used to inquire about the voltage range ne...

Page 534: ...to stop transmission CMD13 ac 31 16 RCA 15 0 stuff bits R1 SEND_STATUS Addressed card sends its status register CMD14 adtc 31 0 stuff bits R1 BUSTEST_R A host reads the reversed bus testing data pattern from a card CMD15 ac 31 16 RCA 15 0 reserved bits GO_INACTIVE_ STATE Sends an addressed card into the Inactive State This command is used when the host explicitly wants to deactivate a card CMD19 a...

Page 535: ...k length is specified the same as READ_SINGLE_BLOCK command Note The transferred data must not cross a physical block boundary unless READ_BLK_MISALIGN is set in the CSD register Table 19 6 Stream read commands class 1 and stream write commands class 3 Cmd index type argument Response format Abbreviation Description CMD11 adtc 31 0 data address R1 READ_DAT_UN TIL_STOP Reads data stream from the ca...

Page 536: ... once The card contains hardware to prevent this operation after the first programming Normally this command is reserved for the manufacturer CMD27 adtc 31 0 stuff bits R1 PROGRAM_C SD Programming of the programmable bits of the CSD Note 1 The data transferred shall not cross a physical block boundary unless WRITE_BLK_MISALIGN is set in the CSD In the case that write partial blocks is not supporte...

Page 537: ...tection are coded in the card specific data WP_GRP_SIZE A High Capacity SD Memory Card does not support this command CMD29 ac 31 0 data address R1b CLR_WRITE_ PROT If the card provides write protection features this command clears the write protection bit of the addressed group CMD30 adtc 31 0 write protect data address R1 SEND_WRITE _PROT If the card provides write protection features this comman...

Page 538: ... ACMD51 adtc 31 0 stuff bits R1 SEND_SCR Reads the SD Configuration Register SCR CMD55 ac 31 16 RCA 15 0 stuff bits R1 APP_CMD Indicates to the card that the next command is an application specific command rather than a standard command CMD56 adtc 31 1 stuff bits 0 RD WR R1 GEN_CMD Used either to transfer a data block to the card or to get a data block from the card for general purpose application...

Page 539: ...hich are not defined in the MMC standard CMD40 bcr 31 0 stuff bits R5 GO_IRQ_STA TE Sets the system into interrupt mode CMD52 adtc 31 R W Flag 30 28 Function Number 27 RAW Flag 26 Stuff Bits 25 9 Register Address 8 Stuff Bits 7 0 Write Data Stuff Bits R5 IO_RW_DIRE CT The IO_RW_DIRECT is the simplest means to access a single register within the total 128K of register space in any I O function incl...

Page 540: ...roup 4 0h or Fh 11 8 reserved for function group 3 0h or Fh 7 4 function group 2 for command system 3 0 function group 1 for access mode R1 SWITCH_FUN C Only for SD memory and SD I O Checks switchable function mode 0 and switch card function mode 1 19 5 3 Responses All responses are sent on the CMD line The response transmission always starts with the left bit of the bit string corresponding to th...

Page 541: ...re protected by a CRC Every command code word is terminated by the end bit always 1 R1 normal response command Code length is 48 bits The bits 45 40 indicate the index of the command to be responded to this value being interpreted as a binary coded number between 0 and 63 The status of the card is coded in 32 bits Note that if a data transfer to the card is involved then a busy signal may appear o...

Page 542: ...C The response of different cards may have a little different Table 19 16 Response R3 Bit position 47 46 45 40 39 8 7 1 0 Width 1 1 6 32 7 1 Value 0 0 111111 x 1111111 1 description start bit transmission bit reserved OCR register reserved end bit R4 Fast I O For MMC only Code length 48 is bits The argument field contains the RCA of the addressed card the register address to be read out or written...

Page 543: ...1 16 of winning card or of the host 15 0 Not defined May be used for IRQ data CRC7 end bit R5b For SD I O only The SDIO card s response to CMD52 and CMD53 is R5 If the communication between the card and host is in the 1 bit or 4 bit SD mode the response shall be in a 48 bit response R5 Table 19 20 Response R5 for SD I O Bit position 47 46 45 40 39 24 23 16 15 8 7 1 0 Width 1 1 6 16 8 8 7 1 Value 0...

Page 544: ...1 description start bit transmission bit CMD8 Reserved bits Voltage accepted echo back of check pattern CRC7 end bit 19 5 4 Data packets format There are 3 data bus mode 1 bit 4 bit and 8 bit width 1 bit mode is mandatory 4 bit and 8 bit mode is optional Although using 1 bit mode DAT3 also need to notify card current working mode is SDIO or SPI when card reset and initialize 1 bit data packet form...

Page 545: ... b5 b4 b7 b6 b5 b4 b7 b6 b5 b4 b3 b2 b1 b0 19 5 5 Two status fields of the card The SD Memory supports two status fields and others just support the first one Card Status Error and state information of an executed command indicated in the response SD Status Extended status field of 512 bits that supports special features of the SD Memory Card and future Application Specific features Card status Th...

Page 546: ...l clear it with a delay of one command C Cleared by read Table 19 23 Card status Bits Identifier Type Value Description Clear Condition 31 OUT_OF_RANGE ERX 0 no error 1 error The command s argument was out of the allowed range for this card C 30 ADDRESS_ERROR ERX 0 no error 1 error A misaligned address which did not match the block length was used in the command C 29 BLOCK_LEN_ERROR ERX 0 no error...

Page 547: ...no error 1 error Internal card controller error C 19 ERROR ERX 0 no error 1 error A general or an unknown error occurred during the operation C 18 UNDERRUN ERX 0 no error 1 error Only for MMC The card could not sustain data transfer in stream read mode C 17 OVERRUN ERX 0 no error 1 error Only for MMC The card could not sustain data programming in stream write mode C 16 CID CSD_OVERWRITE ERX 0 no e...

Page 548: ...te change it will be visible to the host in the response to the next command The four bits are interpreted as a binary coded number between 0 and 15 B 8 READY_FOR_DATA SX 0 not ready 1 ready Corresponds to buffer empty signaling on the bus A 7 SWITCH_ERROR EX 0 no error 1 switch error If set the card don t switch to the expected mode as requested by the SWITCH command B 6 Reserved 5 APP_CMD SR 0 e...

Page 549: ...BUS_WIDTH SR 00 1 default 01 reserved 10 4 bit width 11 reserved Shows the currently defined data bus width that was defined by SET_BUS_WIDTH command A 509 SECURED_MODE SR 0 Not in the mode 1 In Secured Mode Card is in Secured Mode of operation refer to the SD Security Specification A 508 4 96 reserved 495 4 80 SD_CARD_TYPE SR The following cards are currently defined 0000 Regular SD RD WR Card 00...

Page 550: ...SDSC and SDHC SDXC In case of SDSC Card the capacity of protected area is calculated as follows Protected Area SIZE_OF_PROTECTED_AREA_ MULT BLOCK_LEN SIZE_OF_PROTECTED_AREA is specified by the unit in MULT BLOCK_LEN In case of SDHC and SDXC Cards the capacity of protected area is calculated as follows Protected Area SIZE_OF_PROTECTED_AREA SIZE_OF_PROTECTED_AREA is specified by the unit in byte SPE...

Page 551: ...Table 19 26 AU_SIZE field AU_SIZE Value Definition 0h Not Defined 1h 16 KB 2h 32 KB 3h 64 KB 4h 128 KB 5h 256 KB 6h 512 KB 7h 1 MB 8h 2 MB 9h 4 MB Ah 8 MB Bh 12 MB Ch 16 MB Dh 24 MB Eh 32 MB Fh 64 MB The maximum AU size depends on the card capacity is defined in Table 19 26 AU_SIZE field The card can set any AU size specified in Table 19 27 Maximum AU size that is less than or equal to the maximum...

Page 552: ...specified by ERASE_SIZE The range of ERASE_TIMEOUT can be defined as up to 63 seconds and the card manufacturer can choose any combination of ERASE_SIZE and ERASE_TIMEOUT depending on the implementation Once ERASE_TIMEOUT is determined it determines the ERASE_SIZE The host can determine timeout for any number of AU erase by the equation below Erase timeout of X AU TERASE NERASE X TOFFSET 19 1 Tabl...

Page 553: ... Idle State including the cards that have been in Inactive State before After power on or CMD0 all cards CMD lines are in input mode waiting for start bit of the next command The cards are initialized with a default relative card address RCA and with a default driver strength with 400 KHz clock frequency Operating voltage range validation At the start of communication between the host and the card...

Page 554: ...is received then the card is SD Otherwise the card is an MMC or CE ATA 3 Initialization the card according to the card type Use a clock source with a frequency FOD that is 400 KHz and use the following command sequence SD card Send CMD0 ACMD41 CMD2 CMD3 SDHC card send CMD0 CMD8 ACMD41 CMD2 CMD3 SD I O Send CMD52 CMD0 CMD5 if the card doesn t have memory port send CMD3 otherwise send ACMD41 CMD11 o...

Page 555: ...DDRESS_ERROR error bit in the status register and while ignoring all further data transfer The write operation will also be aborted if the host tries to write data on a write protected area In this case however the card will set the WP_VIOLATION bit in the status register Programming of the CID and CSD registers does not require a previous block length setting The transferred data is also CRC prot...

Page 556: ... When a DTEND interrupt is received the data transfer is over For an open ended block transfer if the byte count is 0 the software must send the STOP command If the byte count is not 0 then upon completion of a transfer of a given number of bytes the host should send the STOP command 19 6 4 Single block or multiple block read Block read is block oriented data transfer The basic unit of data transf...

Page 557: ...ld look for data error interrupts If required software can terminate the data transfer by sending a STOP command 6 The software should read data from the FIFO and make space in the FIFO for receiving more data 7 When a DTEND interrupt is received the software should read the remaining data in the FIFO 19 6 5 Stream write and stream read MMC only Stream write Stream write CMD20 starts the data tran...

Page 558: ...CMD12 The stop command has an execution delay due to the serial command transmission The data transfer stops after the end bit of the stop command If the host provides an out of range address as an argument to CMD11 the card will reject the command remain in Transfer state and respond with the ADDRESS_OUT_OF_RANGE bit set Note that the stream read command works only on a 1 bit bus configuration on...

Page 559: ...ND CMD36 ERASE_WR_BLK_END CMD33 command and finally it starts the erase process by issuing the ERASE CMD38 command The address field in the erase commands is an Erase Group address in byte units The card will ignore all LSB s below the Erase Group size effectively rounding the address down to the Erase Group boundary If an erase command CMD35 CMD36 and CMD38 is received out of the defined erase se...

Page 560: ...rotection optional The entire card may be write protected by setting the permanent or temporary write protect bits in the CSD Some cards support write protection of groups of sectors by setting the WP_GRP_ENABLE bit in the CSD It is defined in units of WP_GRP_SIZE erase groups as specified in the CSD The SET_WRITE_PROT command sets the write protection of the addressed write protected group and th...

Page 561: ...ode PWD itself card lock unlock etc Table 19 31 Lock card data structure describes the structure of the command data block Table 19 31 Lock card data structure Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Reserved all set to 0 ERASE LOCK_UNLOCK CLR_PWD SET_PWD 1 PWDS_LEN 2 Password data PWD PWDS_LEN 1 ERASE 1 Defines Forced Erase Operation In byte 0 bit 3 will be set to 1 all other bits ...

Page 562: ...e will be saved in the PWD and PWD_LEN registers respectively Reset the password Select a card CMD7 if not previously selected Define the block length CMD16 given by the 8 bit card lock unlock mode the 8 bit password size in bytes and the number of bytes of the currently used password Send the card lock unlock command with the appropriate data block size on the data line including the 16 bit CRC T...

Page 563: ... the SDIO_DATACTL 11 bit is set except for read suspend that does not need specific hardware implementation SD I O read wait operation The optional Read Wait RW operation is defined only for the SD 1 bit and 4 bit modes The Read Wait operation allows a host to signal a card that is executing a read multiple CMD53 operation to temporarily stall the data transfer while allowing the host to send comm...

Page 564: ...aiting again until it receives data from the card The DSM will not start a Read Wait interval while receiving a block even if Read Wait start is set the Read Wait interval will start after the CRC is received The RWSTOP bit has to be cleared to start a new Read Wait operation During the Read Wait interval the SDIO can detect SD I O interrupts on SDIO_DAT 1 SD I O suspend resume operation Within a ...

Page 565: ... a complete packet just before stopping the data transaction The application should continue reading receive FIFO until the FIFO is empty and the DSM goes Idle state automatically Interrupts In order to allow the SD I O card to interrupt the host an interrupt function is added to a pin on the SD interface Pin number 8 which is used as SDIO_DAT 1 when operating in the 4 bit SD mode is used to signa...

Page 566: ...terrupt during a 4 bit multi block read and Figure 19 18 Multiple block 4 Bit write interrupt cycle timing shows the operation for an interrupt during a 4 bit multi block write Figure 19 17 Multiple block 4 Bit read interrupt cycle timing SDIO_CLK DAT0 Command read data CMD DAT1 DAT1 mode S E Response S E Data S E interrupt data data int Data S E Data S E Data S E int 2 CLK 2 CLK data Figure 19 18...

Page 567: ...st detects a command completion signal from the device it should issue a FAST_IO CMD39 command to read the ATA Status register to determine the ending status for the ATA command Command completion disable signal The host may cancel the ability for the device to return a command completion signal by issuing the command completion signal disable The host shall only issue the command completion signa...

Page 568: ...state card input or output 00 SDIO power off SDIO cmd data state machine reset to IDLE clock to card stopped no cmd data output to card 01 Reserved 10 Reserved 11 SDIO Power on Note Between Two write accesses to this register it needs at least 3 SDIOCLK 2 pclk2 which used to sync the registers to SDIOCLK clock domain 19 8 2 Clock control register SDIO_CLKCTL Address offset 0x04 Reset value 0x0000 ...

Page 569: ...ode selected 10 CLKBYP Clock bypass enable bit This bit defines the SDIO_CLK is directly SDIOCLK or not 0 NO bypass the SDIO_CLK refers to DIV bits in SDIO_CLKCTL register 1 Clock bypass the SDIO_CLK is directly from SDIOCLK SDIOCLK 1 9 CLKPWRSAV SDIO_CLK clock dynamic switch on off for power saving This bit controls SDIO_CLK clock dynamic switch on off when the bus is idle for power saving 0 SDIO...

Page 570: ...ing a command 19 8 4 Command control register SDIO_CMDCTL Address offset 0x0C Reset value 0x0000 0000 The SDIO_CMDCTL register contains the command index and other command control bits to control command state machine This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ATAEN NINTEN ENCMDC SUSPEN D C...

Page 571: ...state machine starts to send a command must wait the end of data transfer 0 no effect 1 Wait the end of data transfer 8 INTWAIT Interrupt wait instead of timeout This bit defines the command state machine to wait card interrupt at CS_Wait state in command state machine If this bit is set no command wait timeout generated 0 Not wait interrupt 1 Wait interrupt 7 6 CMDRESP 1 0 Command response type b...

Page 572: ...0 3 Address offset 0x14 4 x x 0 3 Reset value 0x0000 0000 These register contains the content of the last card response received This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESPx 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESPx 15 0 r Bits Fields Descriptions 31 0 RESPx 31 0 Card state The content of the response see Table 19 32 SDIO_RESPx reg...

Page 573: ...egister and the data length register must be updated before being written to the data control register when need a data transfer 19 8 8 Data length register SDIO_DATALEN Address offset 0x28 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved DATALEN 24 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATALEN 15 0 rw Bits Field...

Page 574: ...specific function enable SD I O only 0 Not SD I O specific function 1 SD I O specific function 10 RWTYPE Read wait type SD I O only 0 Read Wait control using SDIO_DAT 2 1 Read Wait control by stopping SDIO_CLK 9 RWSTOP Read wait stop SD I O only 0 No effect 1 Stop the read wait process if RWEN bit is set 8 RWEN Read wait mode enabled SD I O only 0 Read wait mode is disabled 1 Read wait mode is ena...

Page 575: ...to Readwait state if RWEN is set or to the WaitS WaitR state depend on DATADIR bit Start a new data transfer it not need to clear this bit to 0 Note Between Two write accesses to this register it needs at least 3 SDIOCLK 2 pclk2 which used to sync the registers to SDIOCLK clock domain 19 8 10 Data counter register SDIO_DATACNT Address offset 0x30 Reset value 0x0000 0000 This register is read only ...

Page 576: ...20 19 18 17 16 Reserved ATAEND SDIOINT RXDTVA L TXDTVAL RFE TFE RFF TFF r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFH TFH RXRUN TXRUN CMDRUN DTBLK END STBITE DTEND CMD SEND CMD RECV RXORE TXURE DTTMOU T CMD TMOUT DTCRC ERR CCRCER R r r r r r r r r r r r r r r r r Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 ATAEND CE ATA command completion signal received only...

Page 577: ...rror occurs 3 DTTMOUT Data timeout The data timeout period depends on the SDIO_DATATO register 2 CMDTMOUT Command response timeout The command timeout period has a fixed value of 64 SDIO_CLK clock periods 1 DTCRCERR Data block sent received CRC check failed 0 CCRCERR Command response received CRC check failed 19 8 12 Interrupt clear register SDIO_INTC Address offset 0x38 Reset value 0x0000 0000 Th...

Page 578: ...ag clear bit Write 1 to this bit to clear the flag 6 CMDRECVC CMDRECV flag clear bit Write 1 to this bit to clear the flag 5 RXOREC RXORE flag clear bit Write 1 to this bit to clear the flag 4 TXUREC TXURE flag clear bit Write 1 to this bit to clear the flag 3 DTTMOUTC DTTMOUT flag clear bit Write 1 to this bit to clear the flag 2 CMDTMOUTC CMDTMOUT flag clear bit Write 1 to this bit to clear the ...

Page 579: ...ta valid in receive FIFO interrupt enable Write 1 to this bit to enable the interrupt 20 TXDTVALIE Data valid in transmit FIFO interrupt enable Write 1 to this bit to enable the interrupt 19 RFEIE Receive FIFO empty interrupt enable Write 1 to this bit to enable the interrupt 18 TFEIE Transmit FIFO empty interrupt enable Write 1 to this bit to enable the interrupt 17 RFFIE Receive FIFO full interr...

Page 580: ...bit to enable the interrupt 4 TXUREIE Transmit FIFO underrun error interrupt enable Write 1 to this bit to enable the interrupt 3 DTTMOUTIE Data timeout interrupt enable Write 1 to this bit to enable the interrupt 2 CMDTMOUTIE Command response timeout interrupt enable Write 1 to this bit to enable the interrupt 1 DTCRCERRIE Data CRC fail interrupt enable Write 1 to this bit to enable the interrupt...

Page 581: ...ite to or read from the FIFO 19 8 15 FIFO data register SDIO_FIFO Address offset 0x80 Reset value 0x0000 0000 This register occupies 32 entries of 32 bit words the address offset is from 0x80 to 0xFC This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIFODT 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFODT 15 0 rw Bits Fields Descriptions 31 0 FIFOD...

Page 582: ...ted external memory SRAM PSRAM ROM NOR Flash 8 bit or 16 bit NAND Flash 16 bit PC Card Protocol translation between the AMBA and the multitude of external memory protocol Offering a variety of programmable timing parameters to meet user s specific needs Each bank has its own chip select signal which can be configured independently Independent read write timing configuration to a sub set memory typ...

Page 583: ...ite accesses can be split into several consecutive 8 bit or 16 bit read write operations respectively In the process of data transfer AHB access data width and memory data width may not be the same In order to ensure consistency of data transmission EXMC s read write accesses follows the following basic regulation When the width of AHB bus equals to the memory bus width no conversion is applied Wh...

Page 584: ... 1 2 is each divided into two spaces the attribute memory space and the common memory space Bank3 is divided into three spaces which are the attribute memory space the common memory space and the I O memory space Each bank or region has a separate chip select control signal which can be configured independently Bank0 is used for NOR and PSRAM device access Bank1 and bank2 are used to access NAND F...

Page 585: ...wing rules When data bus width of the external memory is 8 bits in this case the memory address is byte aligned HADDR 25 0 is connected to EXMC_A 25 0 and then the EXMC_A 25 0 is connected to the external memory address lines When data bus width of the external memory is 16 bits in this case the memory address is half word aligned HADDR byte address must be converted into half word aligned by conn...

Page 586: ...FFF FFFF Address Memory Space EXMC Memory Bank NAND address mapping For NAND Flash the common space and the attribute space are further divided into three areas individually the data area the command area and the address area as shown in Figure 20 5 Diagram of bank1 common space Figure 20 5 Diagram of bank1 common space Data Area Command Area Address Area 0x7000 0000 0x7000 FFFF 0x7001 0000 0x7001...

Page 587: ...n the EXMC is in data reception mode software should read the data from the NAND Flash by reading this area Data access address is incremented automatically in consecutive mode users need not to be concerned with access address area 20 3 4 NOR PSRAM controller NOR PSRAM memory controller controls bank0 which is designed to support NOR Flash PSRAM SRAM ROM and honeycomb RAM external memory EXMC has...

Page 588: ...ut Async Sync Data Bus EXMC_NE x Output Async Sync Chip selection x 0 1 2 3 EXMC_NOE Output Async Sync Read enable EXMC_NWE Output Async Sync Write enable EXMC_NWAIT Input Async Sync Wait input signal EXMC_NL NADV Output Async Sync Latch enable address valid enable NADV EXMC_NBL 1 Output Async Sync Upper byte enable EXMC_NBL 0 Output Async Sync Lower byte enable Supported memory access mode Table ...

Page 589: ...2 16 Sync W 8 16 Use of byte lanes EXMC_NBL 1 0 Sync W 16 16 Sync W 32 16 SRAM and ROM Async R 8 8 Async R 8 16 Async R 16 8 Split into 2 EXMC accesses Async R 16 16 Async R 32 8 Split into 4 EXMC accesses Async R 32 16 Split into 2 EXMC accesses Async W 8 8 Async W 8 16 Use of byte lanes EXMC_NBL 1 0 Async W 16 8 Async W 16 16 Async W 32 8 Async W 32 16 NOR Flash PSRAM controller timing EXMC prov...

Page 590: ...DSET ASET Mode C 1 NOR Flash with EXMC_NOE toggling on data phase WDSET WASET DSET ASET Mode D 1 With address hold capability WDSET WAHLD WASET DSET AHLD ASET Mode AM 0 NOR Flash address data mux DSET AHLD ASET BUSLAT DSET AHLD ASET BUSLAT Sync Mode E 0 NOR PSRAM CRAM synchronous read PSRAM CRAM synchronous write DLAT CKDIV DLAT CKDIV Mode SM 0 NOR Flash address data mux DLAT CKDIV DLAT CKDIV As s...

Page 591: ...ccess Address EXMC_A 25 0 Byte Lane Select EXMC_NBL 1 0 Chip Enable EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE Data EXMC_D 15 0 Address Setup Time ASET 1 HCLK Data Setup Time DSET HCLK EXMC Output 1 HCLK Table 20 6 Mode 1 related registers configuration Bit Position Bit Name Reference Setting Value EXMC_SNCTLx 31 20 Reserved 0x000 19 SYNCWR 0x0 18 16 Reserved 0x0 15 ASYNCWAIT Depends on...

Page 592: ...23 20 CKDIV No effect 19 16 BUSLAT Time between EXMC_NE x rising edge to EXMC_NE x falling edge 15 8 DSET Depends on memory and user DSET 1 HCLK for write DSET 3 HCLK for read 7 4 AHLD No effect 3 0 ASET Depends on memory and user Mode A SRAM PSRAM CRAM OE toggling Figure 20 8 Mode A read access Address EXMC_A 25 0 Byte Lane Select EXMC_NBL 1 0 Chip Enable EXMC_NEx Output Enable EXMC_NOE Write Ena...

Page 593: ...nfiguration is independent of its read configuration Table 20 7 Mode A related registers configuration Bit Position Bit Name Reference Setting Value EXMC_SNCTLx 31 20 Reserved 0x000 19 SYNCWR 0x0 18 16 Reserved 0x0 15 ASYNCWAIT Depends on memory 14 EXMODEN 0x1 13 NRWTEN 0x0 12 WREN Depends on user 11 NRWTCFG No effect 10 WRAPEN 0x0 9 NRWTPOL Meaningful only when the bit 15 is set to 1 8 SBRSTEN 0x...

Page 594: ...9 28 WASYNCMOD 0x0 27 24 DLAT No effect 23 20 CKDIV No effect 19 16 Reserved 0x00 15 8 WDSET Depends on memory and user WDSET 1 HCLK for write 7 4 WAHLD 0x0 3 0 WASET Depends on memory and user Mode 2 B NOR Flash Figure 20 10 Mode 2 B read access Address EXMC_A 25 0 Address Valid EXMC_NADV Chip Enable EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE Data EXMC_D 15 0 Memory Output Address Setu...

Page 595: ...C_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE Data EXMC_D 31 0 Address Setup Time WASET 1 HCLK Data Setup Time WDSET HCLK EXMC Output 1 HCLK Table 20 8 Mode 2 B related registers configuration Bit Position Bit Name Reference Setting Value EXMC_SNCTLx Mode 2 Mode B 31 20 Reserved 0x000 19 SYNCWR 0x0 18 16 Reserved 0x0 15 ASYNCWAIT Depends on memory 14 EXMODEN Mode 2 0x0 Mode B 0x1 13 NRWTEN 0x...

Page 596: ...n memory and user DSET 3 HCLK for read 7 4 AHLD 0x0 3 0 ASET Depends on memory and user EXMC_SNWTCFGx Write in mode B 31 30 Reserved 0x0000 29 28 WASYNCMOD Mode B 0x1 27 24 DLAT No effect 23 20 CKDIV No effect 19 16 Reserved 0x000 15 8 WDSET Depends on memory and user WDSET 1 HCLK for write 7 4 WAHLD 0x0 3 0 WASET Depends on memory and user Mode C NOR Flash OE toggling Figure 20 13 Mode C read acc...

Page 597: ... is independent of its read configuration and the toggle of NOE and NADV are different Table 20 9 Mode C related registers configuration Bit Position Bit Name Reference Setting Value EXMC_SNCTLx 31 20 Reserved 0x000 19 SYNCWR 0x0 18 16 Reserved 0x0 15 ASYNCWAIT Depends on memory 14 EXMODEN 0x1 13 NRWTEN 0x0 12 WREN Depends on user 11 NRWTCFG No effect 10 WRAPEN 0x0 9 NRWTPOL Meaningful only when t...

Page 598: ...o effect 23 20 CKDIV No effect 19 16 Reserved 0x0 15 8 WDSET Depends on memory and user WDSET 1 HCLK for write 7 4 WAHLD 0x0 3 0 WASET Depends on memory and user Mode D Asynchronous access with extended address Figure 20 15 Mode D read access Address EXMC_A 25 0 Address Valid EXMC_NADV Chip Enable EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE Data EXMC_D 15 0 Memory Output Address Setup Ti...

Page 599: ...NCTLx 31 20 Reserved 0x000 19 SYNCWR 0x0 18 16 Reserved 0x0 15 ASYNCWAIT Depends on memory 14 EXMODEN 0x1 13 NRWTEN 0x0 12 WREN Depends on user 11 NRWTCFG No effect 10 WRAPEN 0x0 9 NRWTPOL Meaningful only when the bit 15 is set to 1 8 SBRSTEN 0x0 7 Reserved 0x1 6 NREN Depends on memory 5 4 NRW Depends on memory 3 2 NRTP Depends on memory 1 NRMUX 0x0 0 NRBKEN 0x1 EXMC_SNTCFGx 31 30 Reserved 0x0 29 ...

Page 600: ...plex mode read access 1 HCLK Address EXMC_A 25 16 Address Valid EXMC_NADV Chip Enable EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE Data Mux EXMC_D 15 0 Memory Output Address Setup Time ASET 1 HCLK Data Setup Time DSET 1 HCLK Address Hold Time AHLD 1 HCLK Address 15 0 Address 25 16 2 HCLK Figure 20 18 Multiplex mode write access Address EXMC_A 25 16 Address Valid EXMC_NADV Chip Enable EXMC...

Page 601: ...SYNCMOD 0x0 27 24 DLAT No effect 23 20 CKDIV No effect 19 16 BUSLAT Minimum time between EXMC_NE x rising edge to EXMC_NE x falling edge 15 8 DSET Depends on memory and user 7 4 AHLD Depends on memory and user 3 0 ASET Depends on memory and user Wait timing of asynchronous communication Wait feature is controlled by the bit ASYNCWAIT in register EXMC_SNCTLx During extern memory access data setup p...

Page 602: ...IT NRWTPOL 1 2 HCLK Data sampling point Figure 20 20 Write access timing diagram under async wait signal assertion Address EXMC_A 25 0 Wait EXMC_NWAIT NRWTPOL 0 Chip Enable EXMC_NEx Write Enable EXMC_NWE Data EXMC_D 15 0 Address Setup Time Data Setup Time 3 HCLK EXMC Output 1 HCLK Wait EXMC_NWAIT NRWTPOL 1 Synchronous access timing diagram The relations between memory clock EXMC_CLK and system clo...

Page 603: ... signal will be detected after a period of data latency If EXMC_NWAIT signal detected is valid wait cycles will be inserted until EXMC_NWAIT becomes invalid The valid polarity of EXMC_NWAIT NRWTPOL 1 valid level of EXMC_NWAIT signal is high NRWTPOL 0 valid level of EXMC_NWAIT signal is low In synchronous burst mode EXMC_NWAIT signal has two kinds of configurations NRWTCFG 1 When EXMC_NWAIT signal ...

Page 604: ...ffect 11 NRWTCFG Depends on memory 10 WRAPEN 0x0 9 NRWTPOL Depends on memory 8 SBRSTEN 0x1 burst read enable 7 Reserved 0x1 6 NREN Depends on memory 5 4 NRW 0x1 3 2 NRTP Depends on memory 0x1 0x2 1 NRMUX 0x1 Depends on memory and users 0 NRBKEN 0x1 EXMC_SNTCFGx Read 31 30 Reserved 0x0 Address EXMC_A 25 16 Address Valid EXMC_NADV Chip Enable EXMC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE HCL...

Page 605: ...MC_NEx Output Enable EXMC_NOE Write Enable EXMC_NWE HCLK Clock EXMC_CLK Wait EXMC_NWAIT Data EXMC_D 15 0 Address 15 0 Data Latency DATLAT 2 EXMC_CLK Wait Cycle NRWTCFG 0 Address 25 16 EXMC Data 2 EXMC Data 3 Burst write of three half words EXMC Data 1 Table 20 13 Timing configurations of synchronous multiplexed write mode Bit Position Bit Name Reference Setting Value EXMC_SNCTLx 31 20 Reserved 0x0...

Page 606: ...nfiguration 8 bit and 16 bit NAND Flash and 16 bit PC Card are supported An ECC hardware is provided for the NAND Flash controller to ensure the robustness of data transfer and storage NAND Flash or PC Card interface function Table 20 14 8 bit or 16 bit NAND interface signal EXMC Pin Direction Functional description EXMC_A 17 Output NAND Flash address latch ALE EXMC_A 16 Output NAND Flash command ...

Page 607: ... size Comments 8 bit NAND Async R 8 Async W 8 Async R 16 Automatically split into 2 EXMC accesses Async W 16 Async R 32 Automatically split into 4 EXMC accesses Async W 32 16 bit NAND PC Card Async R 8 Async W 8 Not support this operation Async R 16 Async W 16 Async R 32 Automatically split into 2 EXMC accesses Async W 32 NAND Flash or PC Card controller timing EXMC can generate the appropriate si...

Page 608: ... which are defined in the common memory space operations The programmable parameters of Attribute memory space or I O memory space only for PC Card are defined as well Figure 20 23 Access timing of common memory space of PC Card Controller Chip Enable EXMC_NCE EXMC_NREG EXMC_NIORD EXMC_NIOWR Clock EXMC_CLK Address EXMC_A 25 0 EXMC_NWE EXMC_NOE Write Data Read Data COMSETx 1 HCLK COMHIZx HCLK COMWA...

Page 609: ... and address in step 2 NAND Flash pre wait functionality Some NAND Flash requires that the controller should wait for NAND Flash to be busy after the first command byte following the address bytes are sent and some EXMC_NCE sensitive NAND Flash also requires that the EXMC_NCE must remain valid before it is ready Taking TOSHIBA128 M x 8 bit NAND Flash as an example Figure 20 24 Access to none NCE d...

Page 610: ...g ECCEN bit of EXMC_NPCTLx register to zero and then restart ECC calculation by setting the ECCEN bit of EXMC_NPCTLx to 1 PC CF Card access EXMC Bank3 is used exclusively for PC CF Card both memory and IO mode access are supported This bank is divided further into three sub spaces memory attribute and IO space EXMC_NCE3_0 and EXMC_NCE3_1 are the byte select signals when only EXMC_NCE3_0 is active ...

Page 611: ...ted EXMC_NOE and EXMC_NWE are the read and write enable signal for this type of access 2 Attribute space It is usually where configuration information are stored for byte AHB access only even address is possible Half word access converts into a single byte access automatically and word access is converted into two consecutive byte access where only the even bytes are operational In both half word ...

Page 612: ...erved NREN NRW 1 0 NRTP 1 0 NRMUX NRBKEN rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 20 Reserved Must be kept at reset value 19 SYNCWR Synchronous write 0 Asynchronous write 1 Synchronous write 18 16 Reserved Must be kept at reset value 15 ASYNCWAIT Asynchronous wait 0 Disable the asynchronous wait function 1 Enable the asynchronous wait function 14 EXMODEN Extended mode ena...

Page 613: ...rved Must be kept at reset value 6 NREN NOR Flash access enable 0 Disable NOR Flash access 1 Enable NOR Flash access 5 4 NRW 1 0 NOR region memory data bus width 00 8 bits 01 16 bits default after reset 10 11 Reserved 3 2 NRTP 1 0 NOR region memory type 00 SRAM default after reset for region1 region3 01 PSRAM CRAM 10 NOR Flash default after reset for region0 11 Reserved 1 NRMUX NOR region memory a...

Page 614: ...s access 0x0 Data latency of first burst access is 2 EXMC_CLK 0x1 Data latency of first burst access is 3 EXMC_CLK 0xF Data latency of first burst access is 17 EXMC_CLK 23 20 CKDIV 3 0 Synchronous clock divide ratio This filed is only effect in synchronous mode 0x0 Reserved 0x1 EXMC_CLK period 2 HCLK period 0xF EXMC_CLK period 16 HCLK period 19 16 BUSLAT 3 0 Bus latency The bits are defined in mul...

Page 615: ...value 0x0FFF FFFF This register has to be accessed by word 32 bit This register is meaningful only when the EXMODEN bit in EXMC_SNCTLx is set to 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved WASYNCMOD 1 0 DLAT 3 0 CKDIV 3 0 Reserved rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDSET 7 0 WAHLD 3 0 WASET 3 0 rw rw rw Bits Fields Descriptions 31 30 Reserved Must be kept at reset value ...

Page 616: ...ld is used to set the time of address hold phase which only used in mode D and multiplexed mode 0x0 Reserved 0x1 Address hold time 2 HCLK 0xF Address hold time 16 HCLK 3 0 WASET 3 0 Address setup time This field is used to set the time of address setup phase Note Meaningful only in asynchronous access of SRAM ROM NOR Flash 0x0 Address setup time 1 HCLK 0x1 Address setup time 2 HCLK 0xF Address set...

Page 617: ...1 HCLK 0xF ALE to RE delay 16 HCLK 12 9 CTR 3 0 CLE to RE delay 0x0 CLE to RE delay 1 HCLK 0x1 CLE to RE delay 2 HCLK 0xF CLE to RE delay 16 HCLK 8 7 Reserved Must be kept at reset value 6 ECCEN ECC enable 0 Disable ECC and reset EXMC_NECCx 1 Enable ECC 5 4 NDW 1 0 NAND bank memory data bus width 00 8 bits 01 16 bits Others Reserved Note for PC CF card 16 bit bus width must be selected 3 NDTP NAND...

Page 618: ...should read the ECC register only after the FIFO empty status flag is raised 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FFEPT INTFEN INTHEN INTREN INTFS INTHS INTRS r rw rw rw rw rw rw Bits Fields Description 31 7 Reserved Must be kept at reset value 6 FFEPT FIFO empty flag 0 FIFO is not empty 1 FIFO is empty 5 INTFEN Interrupt falling e...

Page 619: ...ce for 16 bit PC Card CF card and NAND Flash 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 COMHIZ 7 0 COMHLD 7 0 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMWAIT 7 0 COMSET 7 0 rw rw Bits Fields Description 31 24 COMHIZ 7 0 Common memory data bus HiZ time The bits are defined as time of bus keep high impedance state after writing the data 0x00 COMHIZ 1 HCLK 0xFE COMHIZ 255 HCLK 0xFF COMHIZ 25...

Page 620: ...It is used for 8 bit accesses to the attribute memory space of the PC Card or to access the NAND Flash for the last address or command write access if another timing must be applied 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ATTHIZ 7 0 ATTHLD 7 0 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATTWAIT 7 0 ATTSET 7 0 rw rw Bits Fields Description 31 24 ATTHIZ 7 0 Attribute memory data bus HiZ time...

Page 621: ...timing configuration register EXMC_PIOTCFG3 Address offset 0xB0 Reset value 0xFCFC FCFC This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IOHIZ 7 0 IOHLD 7 0 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IOWAIT 7 0 IOSET 7 0 rw rw Bits Fields Description 31 24 IOHIZ 7 0 IO space data bus HiZ time The bits are defined as time of bus keep high impedance st...

Page 622: ...d 0x00 IOSET 1 HCLK 0xFF IOSET 256 HCLK NAND Flash ECC registers EXMC_NECCx x 1 2 Address offset 0x54 0x20 x x 1 2 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ECC 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ECC 15 0 r Bits Fields Description 31 0 ECC 31 0 ECC result ECCSZ 2 0 NAND Flash page size byte ECC bits 0b000 256 ...

Page 623: ...ides which mailbox will be transmitted firstly Three complete messages can be stored in every FIFO The FIFOs are managed completely by hardware Two receiving FIFOs are used by hardware to store the incoming messages In addition the CAN controller provides all hardware functions which supports the time triggered communication option in safety critical applications 21 2 Characteristics Supports CAN ...

Page 624: ...e Initial working mode Normal working mode Sleep working mode Sleep working mode is the default mode after reset In sleep working mode the CAN is in the low power status and the CAN clock is stopped When SLPWMOD bit in CAN_CTL register is set the CAN enters the sleep working mode Then the SLPWS bit in CAN_STAT register is set by hardware To leave sleep working mode automatically the AWU bit in CAN...

Page 625: ...and SLPWMOD bit in CAN_ CTL register Normal working mode to sleep working mode Set SLPWMOD bit in CAN_CTL register and wait the current transmission or reception completed Normal working mode to Initial working mode Set IWMOD bit in CAN_CTL register and wait the current transmission or reception completed 21 3 2 Communication modes The CAN interface has four communication modes Silent communicatio...

Page 626: ...twork while the transmitted messages are transferred into the RX FIFOs Setting LCMOD and SCMOD bit in CAN_BT register to enter loopback and silent communication mode while clearing them to leave Loopback and silent communication mode is useful on self test The TX pin holds in recessive state The RX pin holds high impedance state Normal communication mode Normal communication mode is the default co...

Page 627: ...arts transmitting the message transmit state After the message has been sent the mailbox is free empty state As shown in Figure 21 3 State of transmission mailbox Figure 21 3 State of transmission mailbox empty pending scheduled transmit Transmit status and error The CAN_TSTAT register includes the transmit status and error bits MTF MTFNERR MAL MTE MTF mailbox transmits finished Typically MTF is s...

Page 628: ...In case that the transmission is failed the state changes to be scheduled and then the abort of transmission can be done immediately Priority When more than one transmit mailbox is pending the transmission order is given by the TFO bit in CAN_CTL register In case that TFO is 1 the three transmit mailboxes work first in first out FIFO In case TFO is 0 the transmit mailbox with lowest identifier has...

Page 629: ...OMDATA10 registers After reading the current frame set RFD bit in CAN_RFIFO0 to release a frame in the Rx FIFO and the software can read the next frame RX FIFO status RFL Rx FIFO length bits in CAN_RFIFOx register is 0 when no frame is stored in the Rx FIFO and it is 3 when FIFOx is full When RFF bit in CAN_RFIFOx register is set it indicates FIFOx is full at this time RFL is 3 When a new frame ar...

Page 630: ... 21 5 32 bit filter FDATA 31 21 FDATA 20 3 FDATA 2 0 SFID 10 0 EFID 17 0 FF FT 0 16 bit SFID 10 0 FT FF and EFID 17 15 bits As shown in Figure 21 6 16 bit filter Figure 21 6 16 bit filter FDATA 31 21 FDATA 20 16 SFID 10 0 FT FF EFID 17 15 FDATA 15 5 FDATA 4 0 SFID 10 0 FT EFID 17 15 FF Mask mode For the Identifier of a data frame to be filtered the mask mode is used to specify which bits must be t...

Page 631: ...er Filter consists of some filter bank According to the mode and the scale of each of the filter banks filter has different effect For example there are two filter banks Bank 0 is configured as 32 bit mask mode Bank 1 is configured as 32 bit list mode The filter number is shown in Table 21 1 32 bit filter number Table 21 1 32 bit filter number Filter Bank Filter Data Register Filter Number 0 F0DAT...

Page 632: ...ATA1 32bit Mask F3DATA1 15 0 16bit ID 4 5 F5DATA0 32bit ID No 3 F3DATA1 31 16 16bit Mask F5DATA1 32bit ID 4 7 F7DATA0 15 0 16bit ID No 5 6 F6DATA0 15 0 16bit ID Yes 5 F7DATA0 31 16 16bit ID 6 F6DATA0 31 16 16bit ID 6 F7DATA1 15 0 16bit ID 7 F6DATA1 15 0 16bit ID 7 F7DATA1 31 16 16bit ID 8 F6DATA1 31 16 16bit ID 8 8 F8DATA0 15 0 16bit ID Yes 9 10 F10DATA0 15 0 16bit ID No 9 F8DATA0 31 16 16bit ID 1...

Page 633: ...ure or bus error the CAN bus controller does not automatically resend the data as usual At the end of sending the MTF bit of register CAN_TSTAT is hardware set to 1 and the sending status information can be obtained via MTFNERR MAL and MTE Bit time On the bit level the CAN protocol uses synchronous bit transmission This not only enhances the transmitting capacity but also requires a sophisticated ...

Page 634: ...negative phase drifts The bit time is shown as in the Figure 21 11 The bit time Figure 21 11 The bit time Sync segment Propagation delay segment Phase buffer segment 1 Phase buffer segment2 Normal Bit Time CAN protocol SYNG_SEG BIT SEGMENT 1 BS1 BIT SEGMENT 2 BS2 CAN The resynchronization Jump Width SJW it can be lengthened or shortened to compensate for the Synchronization error of the CAN networ...

Page 635: ...configuration in register CAN_CTL there are two ways to recover from Bus Off to an error active state Both of these methods require the CAN bus controller in the Bus Offstate to detect the Bus Off recovery sequence defined by CAN protocol when CAN_RX detects 128 consecutive 11 bit recessive bits before automatic recovery If ABOR is set it will be automatically recovered when a offline recovery seq...

Page 636: ...Receive FIFO1 interrupt The receive FIFO1 interrupt can be generated by the following conditions RX FIFO1 not empty RFL1 bits in the CAN_RFIFO1 register are not 00 and RFNEIE1 in CAN_INTEN register is set RX FIFO1 full RFF1 bit in the CAN_RFIFO1 register is set and RFFIE1 in CAN_INTEN register is set RX FIFO1 overrun RFO1 bit in the CAN_RFIFO1 register is set and RFOIE1 in CAN_INTEN register is se...

Page 637: ...G_CTL0 register is set this bit defines the CAN controller is in debug freezing mode or normal working mode If the CANx_HOLD in DBG_CTL0 register is cleared this bit takes no effect 0 CAN reception and transmission work normal even during debug 1 CAN reception and transmission stop working during debug 15 SWRST Software reset 0 No effect 1 Reset CAN to enter sleep working mode This bit is automati...

Page 638: ...e frame the smaller identifier has higher priority 1 Order with first in and first out 1 SLPWMOD Sleep working mode If this bit is set by software the CAN enters sleep working mode after current transmission or reception is completed This bit can be cleared by software or hardware If AWU bit in CAN_CTL register is set this bit is cleared by hardware when CAN bus activity is detected 0 Disable slee...

Page 639: ... to this bit 0 Wakeup event is not coming 1 Wakeup event is coming 2 ERRIF Error interrupt flag This bit is set by the following events The BOERR bit in CAN_ERR register is set and BOIE bit in CAN_INTEN register is set Or the PERR bit in CAN_ERR register is set and PERRIE bit in CAN_INTEN register is set Or the WERR bit in CAN_ERR register is set and WERRIE bit in CAN_INTEN register is set Or the ...

Page 640: ...ial working mode 21 4 3 Transmit status register CAN_TSTAT Address offset 0x08 Reset value 0x1C00 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TMLS2 TMLS1 TMLS0 TME2 TME1 TME0 NUM 1 0 MST2 Reserved MTE2 MAL2 MTFNER R2 MTF2 r r r r r r r rs rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MST1 Reserved MTE1 MAL1 MTFNER R1 MTF1 MST...

Page 641: ...curs This bit is reset by writing 1 to this bit or MTF2 bit in CAN_TSTAT register This bit is reset by hardware when next transmit starts 18 MAL2 Mailbox 2 arbitration lost This bit is set when the arbitration lost occurs This bit is reset by writting 1 to this bit or MTF2 bit in CAN_TSTAT register This bit is reset by hardware when next transmit starts 17 MTFNERR2 Mailbox 2 transmit finished with...

Page 642: ... This bit is set by hardware when the transmission finishes or aborts This bit is reset by writting 1 to this bit or TEN bit in CAN_TMI1 is 1 0 Mailbox 1 transmit is progressing 1 Mailbox 1 transmit finished 7 MST0 Mailbox 0 stop transmitting This bit is set by the software to stop mailbox 0 transmitting This bit is reset by the hardware when the mailbox 0 is empty 6 4 Reserved Must be kept at res...

Page 643: ... 0 Reserved RFD0 RFO0 RFF0 Reserved RFL0 1 0 rs rc_w1 rc_w1 r Bits Fields Descriptions 31 6 Reserved Must be kept at reset value 5 RFD0 Rx FIFO0 dequeue This bit is set by software to start dequeuing a frame from Rx FIFO0 This bit is reset by hardware when the dequeuing is done 4 RFO0 Rx FIFO0 overfull This bit is set by hardware when Rx FIFO0 is overfull and reset by software when writting 1 to t...

Page 644: ...is reset by hardware when the dequeuing is done 4 RFO1 Rx FIFO1 overfull This bit is set by hardware when Rx FIFO1 is overfull and reset by writting 0 to this bit 0 The Rx FIFO1 is not overfull 1 The Rx FIFO1 is overfull 3 RFF1 Rx FIFO1 full This bit is set by hardware when Rx FIFO1 is full and reset by writting 1 to this bit 0 The Rx FIFO1 is not full 1 The Rx FIFO1 is full 2 Reserved Must be kep...

Page 645: ...served Must be kept at reset value 11 ERRNIE Error number interrupt enable 0 Error number interrupt disabled 1 Error number interrupt enabled 10 BOIE Bus Off interrupt enable 0 Bus Off interrupt disabled 1 Bus Off interrupt enabled 9 PERRIE Passive error interrupt enable 0 Passive error interrupt disabled 1 Passive error interrupt enabled 8 WERRIE Warning error interrupt enable 0 Warning error int...

Page 646: ...bled 1 Transmit mailbox empty interrupt enabled 21 4 7 Error register CAN_ERR Address offset 0x18 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RECNT 7 0 TECNT 7 0 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ERRN 2 0 Reserved BOERR PERR WERR rw r r r Bits Fields Descriptions 31 24 RECNT 7 0 Receive error count defined...

Page 647: ...are 21 4 8 Bit timing register CAN_BT Address offset 0x1C Reset value 0x0123 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SCMOD LCMOD Reserved SJW 1 0 Reserved BS2 2 0 BS1 3 0 rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BAUDPSC 9 0 rw Bits Fields Descriptions 31 SCMOD Silent communication mode 0 Silent communication disabled...

Page 648: ...as to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SFID 10 0 EFID 28 18 EFID 17 13 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFID 12 0 FF FT TEN rw rw rw rw Bits Fields Descriptions 31 21 SFID 10 0 EFID 28 1 8 The frame identifier SFID 10 0 Standard format frame identifier EFID 28 18 Extended format frame identifier 20 16 EFID 17 13 The frame identifier EFID 17 13 E...

Page 649: ...ved DLENC 3 0 rw rw Bits Fields Descriptions 31 16 TS 15 0 Time stamp The time stamp of frame in transmit mailbox 15 9 Reserved Must be kept at reset value 8 TSEN Time stamp enable 0 Time stamp disabled 1 Time stamp enabled The TS 15 0 will be transmitted in the DB6 and DB7 in DL This bit is available when the TTC bit in CAN_CTL is set 7 4 Reserved Must be kept at reset value 3 0 DLENC 3 0 Data le...

Page 650: ...18C 0x19C 0x1AC Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DB7 7 0 DB6 7 0 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DB5 7 0 DB4 7 0 rw rw Bits Fields Descriptions 31 24 DB7 7 0 Data byte 7 23 16 DB6 7 0 Data byte 6 15 8 DB5 7 0 Data byte 5 7 0 DB4 7 0 Data byte 4 21 4 13 Receive FIFO mailbox identifier register CAN_RFI...

Page 651: ...fier 15 3 EFID 12 0 The frame identifier EFID 12 0 Extended format frame identifier 2 FF Frame format 0 Standard format frame 1 Extended format frame 1 FT Frame type 0 Data frame 1 Remote frame 0 Reserved Must be kept at reset value 21 4 14 Receive FIFO mailbox property register CAN_RFIFOMPx x 0 1 Address offset 0x1B4 0x1C4 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31...

Page 652: ...ssed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DB3 7 0 DB2 7 0 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DB1 7 0 DB0 7 0 r r Bits Fields Descriptions 31 24 DB3 7 0 Data byte 3 23 16 DB2 7 0 Data byte 2 15 8 DB1 7 0 Data byte 1 7 0 DB0 7 0 Data byte 0 21 4 16 Receive FIFO mailbox data1 register CAN_RFIFOMDATA1x x 0 1 Address offset 0x1BC 0x1CC Reset value 0xXXXX XXXX This regis...

Page 653: ... 6 5 4 3 2 1 0 Reserved FLD rw rw The filter control register with GD32F10x CL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved HBC1F 5 0 Reserved FLD rw rw Bits Fields Descriptions 31 14 Reserved Must be kept at reset value 13 8 HBC1F 5 0 Header bank of CAN1 filter These bits are set and cleared by software to define the first bank for CAN1 f...

Page 654: ... rw rw rw rw rw rw rw Bits Fields Descriptions 31 28 Reserved Must be kept at reset value 27 0 FMODx Filter mode 0 Filter x with mask mode 1 Filter x with list mode 21 4 19 Filter scale configuration register CAN_FSCFG Just for CAN0 Address offset 0x20C Reset value 0x0000 0000 This register has to be accessed by word 32 bit This register can be modified only when FLD bit in CAN_FCTL register is se...

Page 655: ... rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 28 Reserved Must be kept at reset value 27 0 FAFx Filter associated FIFO 0 Filter x associated with FIFO0 1 Filter x associated with FIFO1 21 4 21 Filter working register CAN_FW Just for CAN0 Address offset 0x21C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 656: ... 22 21 20 19 18 17 16 FD31 FD30 FD29 FD28 FD27 FD26 FD25 FD24 FD23 FD22 FD21 FD20 FD19 FD18 FD17 FD16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FD15 FD14 FD13 FD12 FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 0 FDx Filter data Mask mode 0 Mask match disable 1 Mask match enab...

Page 657: ...C automatically transmits pause frame or back pressure feature depending on fill level of RxFIFO in Full duplex mode or in Half duplex mode Automatic transmission of pause frame on assertion and de assertion of flow control input frame Zero quanta pause time length frame for Full duplex operation IEEE 802 3x flow control for Full duplex operation support Back pressure feature to the MAC core based...

Page 658: ...etween reception and transmission controller PTP Feature Support IEEE 1588 time synchronization function Support two correction methods Coarse or Fine Pulse per second output Preset target time reaching trigger and interrupt 22 2 1 Block diagram The Ethernet module is composed of a MAC module MII RMII module and a DMA module by descriptor control Figure 22 1 ENET module block diagram AHB Arbiter M...

Page 659: ...ed 22 2 2 MAC 802 3 Ethernet packet description Data communication of MAC can use two frame formats Basic MAC frame format Tagged MAC frame format extension of the basic MAC frame format Figure 22 2 MAC Tagged MAC frame format describes the structure of the frame Basic and Tagged that includes the following fields Figure 22 2 MAC Tagged MAC frame format Preamble SFD Destination address Source addr...

Page 660: ...Hz MDC MDC ETH_MII_TXD2 PC2 AF output push pull highspeed 50 MHz TXD2 ETH_MII_TX_CLK PC3 Floating input reset state TX_CLK ETH_MII_CRS PA0 Floating input reset state CRS ETH_RX_CLK ETH_RMII_REF_CLK PA1 Floating input reset state RX_CLK REF_CLK ETH_MDIO PA2 AF output push pull highspeed 50 MHz MDIO MDIO ETH_MII_COL PA3 Floating input reset state COL ETH_MII_RX_DV ETH_RMII_CRS_DV PA7 Floating input ...

Page 661: ...erface MII or RMII mode is selected by software and carry on the PHY management through the SMI interface SMI Station management interface SMI is designed to access and configure PHY s configuration Station management interface SMI is performed through two wires to communicate with the external PHY one clock line MDC and one data line MDIO it can access to the any PHY register The interface suppor...

Page 662: ...mode 2 Set PB bit to start reception In the process of transaction PB is always high until the transfer is complete Hardware will clear PB bit automatically The application can be aware of whether a transaction is complete or not through checking PB bit When PB is 1 it means the application should not change the PHY address register contents and the PHY data register contents because of operation ...

Page 663: ..._ER RX_CLK RXD 3 0 CRS COL MII_TX_CLK clock signal for transmitting data For the data transmission speed of 10Mbit s the clock is 2 5MHz for the data transmission speed of 100Mbit s the clock is 25MHz MII_RX_CLK Clock signal for receiving data For the data transmission speed of 10Mbit s the clock is 2 5MHz for the data transmission speed of 100Mbit s the clock is 25MHz MII_TX_EN Transmission enabl...

Page 664: ...nously with the first 4 bit of the frame and must remain asserted while all bits to be transmitted are presented on the MII It must be de asserted prior to the first clock cycle that follows the final 4 bit In order to receive the frame correctly the effective signal starting no later than the SFD field MII_RX_ER Receive error signal It must be asserted for one or more RX clock to indicate MAC det...

Page 665: ...face MII or RMII is selected the bit order of transmit receive is LSB first The deference between MII and RMII is bit number and sending times MII is low 4bits first and then high 4bits but RMII is the lowest 2bits low 2bits high 2bits and the highest 2bits For example a byte value is 10011101b left to right order high to low Transmission order for MII use 2 cycles 1101 1001 left to right order hi...

Page 666: ...the TxDMA fetches the transmit frames from system memory and pushes them into the TxFIFO then the data in TxFIFO are poped to MAC for sending on MII RMII interface The method of popping is according to the selected TxFIFO mode Cut Through mode or Store and Forward mode the specific definition see the next paragraph For convenient application can configure automatically hardware calculated CRC and ...

Page 667: ...e the MAC for automatically adding a load of content of 0 bit to make the byte length of frame s data field in accordance with the relevant domain of definition of IEEE802 3 specification At the same time if automatically adding zeros function is performed the MAC will certainly calculate CRC value of the frame and append it to the frame s FCS field domain no matter what configuration of DCRC bit ...

Page 668: ...nd the pause control frame in Full duplex mode for flow control Half duplex mode flow control Back Pressure When MAC is configured in Half duplex mode there are two conditions to trigger the back pressure feature Both of the two conditions are triggered to enable back pressure function which is implemented by sending a special pattern called jam pattern 0x5555 5555 once to notify conflict to all o...

Page 669: ...ll check RxFIFO again If the byte number in RxFIFO is also greater than active threshold value the MAC sends a pause time again When the byte number of RxFIFO is lower than the de active threshold value MAC maybe send a pause frame with zero time value in frame s pause time field if DZQP bit in ENET_MAC_FCTL register is reset This zero pause time frame can inform send station that RxFIFO is almost...

Page 670: ...load module marks the frame as IPv4 package and calculated value replace the checksum field in frame Because of IPv6 frame header does not contain checksum field the module will not change any value of the IPv6 s header field After IP header checksum calculation end the result is stored in IPHE bit bit 16 in TDES0 The following shows the conditions under which the IPHE bit can be set 1 For IPv4 fr...

Page 671: ...ata will be discarded as padding bytes If the first condition of IPPE error is detected the value of the checksum does not insert a TCP UDP or ICMP header If the second condition of IPPE error is detected checksum calculation results will still insert the appropriate header fields Note For ICMP packets over IPv4 frame the checksum field in the ICMP packet must always be 0x0000 in both modes due to...

Page 672: ...rame s destination address 2 Using the high 6 bits of the calculated CRC value as the index to retrieve the hash list If the corresponding value of hash list is 1 the received frame passes through the filter conversely fail the filter The advantage of this type of filter is that it can cover any possible address just using a small table But the disadvantage is that the filter is imperfect and some...

Page 673: ...tion Reverse filtering operation MAC can reverse filter match result at the final output whether the destination address filtering or source address filtering By setting the DAIFLT and SAIFLT bits in ENET_MAC_FRMF register this address filter reverse function can be enabled DAIFLT bit is used for unicast and multicast frames DA filtering result SAIFLT bit is used for unicast and multicast frames S...

Page 674: ...perfect group filter match and drop frames that fail Promiscuous mode If the PM bit in ENET_MAC_FRMF register is set promiscuous mode is enable Then the address filter function is bypassed all frames are thought passed through the filter At the same time the receive status information DA SA error bit is always 0 Pause control frame filter When MAC received pause frame it will detect 6 bytes DA fie...

Page 675: ...g out data from RxFIFO when the number of FIFO is greater than threshold value RTHC bits in ENET_DMA_CTL register After all data of a frame pop out receive status word is sent to DMA for writing back to descriptor In this mode if a frame has started to forward to application by DMA from FIFO the forwarding will continue until the frame is end even if frame error is detected Although the error fram...

Page 676: ...flects the header checksum result This bit is set if received IP header has the following errors Any mismatch between the IPv4 calculation result by checksum offload module and the value in received frame s checksum field Any inconsistent between the data type of Ethernet type field and IP header version field Received frame length is less than the length indicated in IPv4 header length field or I...

Page 677: ... FIFO overflow or dynamically modify the filter value in the receiving process resulting did not pass the filter etc frame data is not written to FIFO completely MAC loopback mode Often loopback mode is used for testing and debugging hardware and software system for application The MAC loopback mode is enabled by setting the LBM bit in ENET_MAC_CFG register In this mode the MAC transmitter sends t...

Page 678: ...on can choose one of or both of the two methods mentioned above Setting WFEN bit in ENET_MAC_WUM register can make Ethernet wakeup if a remote wakeup frame received and setting MPE bit in ENET_MAC_WUM register can make Ethernet wakeup if a Magic Packet frame is received When any type of wakeup frame is present on interface and corresponding wakeup function is enabled Ethernet will generate a wakeu...

Page 679: ...it m m means byte number is set the filter n offset m of the receiving frame is calculated by the CRC unit conversely filter n offset m is ignored Filter n command This four bits command controls the operation of the filter n The bit 3 of the field is address type selection bit If this bit is 1 the detection only detects a multicast frame and if this bit is 0 the detection only detects a unicast f...

Page 680: ...EFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF AABB CCDD EEFF MISC FCS Upon detecting a Magic Packet the MPKR bit in ENET_MAC_WUM register will be set If the Magic Packet interrupt is enabled the corresponding interrupt will generate Precautions during system power down state When the MCU is in Deep sleep mode if external...

Page 681: ...he MCU system clock enable HXTAL and configure the RCU unit 22 3 5 Precision time protocol PTP The majority of protocols are implemented by the UDP layer application software The PTP module of the MAC is mainly to recording the transmitting and receiving PTP packets precision time and returning it to application Specific details about the precise time protocol PTP please see the document IEEE Stan...

Page 682: ...clock without unpredictability large jitter This method is referred to the value of ENET_PTP_TSADDEND added to the accumulator in each HCLK cycle PTP module will produce a pulse to increase the value of ENET_PTP_TSL register when the accumulator overflowed The increased value when this pulse occurs is in ENET_PTP_SSINC register Figure 22 7 System time update using the fine correction method shows ...

Page 683: ... confirmed by the algorithm after a few Sync cycles Algorithm is as follows Define the master sends a SYNC message to slave time MSYNCT n Define the slave local time SLOCALT n Define the master local time MLOCALT n Calculation MLOCALT n MSYNCT n Master to Slave Delay n Define the master clock count number between two SYNC message sent MCLOCKC n Calculation MCLOCKC n MLOCALT n MLOCALT n 1 Define th...

Page 684: ...imestamp update high and low registers 2 Set bit 3 TMSSTU in the ENET_PTP_TSCTL register to update the timestamp register 3 Poll TMSSTU bit until it is cleared System time update steps under fine correction method 1 Calculate the value of the desired system clock rate corresponding to the addend register calculation formula has explained before 2 Program the addend register and set the bits 5 in E...

Page 685: ...ve clock and the master clock both of the slave and master can output PPS and connect them to one oscilloscope for clock measurement 22 3 6 DMA controller description Ethernet DMA controller is designed for frame transmission between FIFO and system memory which can reduce the occupation of CPU Communication between the CPU and the DMA is achieved by the following two kinds of data structures Desc...

Page 686: ...eds to set the bit 21 in TDES0 or bit 15 in RDES1 to inform DMA the current descriptor is the last one of the table in ring structure At this time the next descriptor pointer points back to the first descriptor address of the descriptor table In chain structure can also set TDES3 or RDES3 value to point back to the first descriptor address of the descriptor table The DMA skips to the next frame bu...

Page 687: ...en the DMA controller reads a descriptor with LSG bit in TDES0 is set it know the current buffers is pointing to the last part of the current frame Normally one frame is stored only in one buffer because buffer size is large enough for a normal frame so FSG bit and LSG bit are set in the same descriptor For the frame receiving process the receive buffer size must be word align But for word align b...

Page 688: ...teps 1 Set the bus access parameters by writing the ENET_DMA_BCTL register 2 Mask unnecessary interrupt source by configuring the ENET_DMA_INTEN register 3 Program the Tx and Rx descriptor table start address by writing the ENET_DMA_TDTADDR register and the ENET_DMA_RDTADDR register 4 Configure filter option by writing related registers 5 According to the auto negotiation result with external PHY ...

Page 689: ...MA controller continues polling the descriptor table until the EOF data LSG bit is set is transferred If the LSG bit of current descriptor is reset it will be closed by resetting the DAV bit after all buffer data pushed into TxFIFO Then the TxDMA controller waits to write back descriptor status and IEEE 1588 timestamp value if enabled 7 After the whole frame is transferred the transmit status bit ...

Page 690: ...ntroller enters in suspend state and the next operation goes to Step 7 7 In suspend state when the status information and timestamp value if the function is enable of the transmitting frame is available the TxDMA controller writes them back to descriptor and then close it by setting DAV 0 of descriptor 8 In suspend state application can make TxDMA returns to running state by writing any data to EN...

Page 691: ... Though the DMA entered suspend state the descriptor pointer is maintained to the descriptor following of the last closed descriptor The DMA controller fetches a descriptor with DAV 0 then it enters suspend state and stops polling In this case the NI bit and TBU bit in ENET_DMA_STAT register are set The MAC FIFO is empty during sending a frame on interface which means an error of underflow occurs ...

Page 692: ...fer allocated in the descriptor is read completely This bit of the frame s first descriptor must be set after all subsequent descriptors belonging to the same frame have been set 0 The descriptor is available for CPU not for DMA 1 The descriptor is available for DMA not for CPU 30 INTC Interrupt on completion bit This is valid only when the last segment TDES0 29 is set 0 TS bit in ENET_DMA_STAT is...

Page 693: ...hecksum calculation and insertion 0x2 Enable IP header checksum and payload checksum calculation and insertion pseudo header checksum is not calculated in hardware 0x3 Enable IP Header checksum and payload checksum calculation and insertion pseudo header checksum is calculated in hardware 21 TERM Transmit end for ring mode bit This bit is used only in ring mode and has higher priority than TCHM 0 ...

Page 694: ...TDES0 12 IP payload error TDES0 11 Loss of carrier TDES0 10 No carrier TDES0 9 Late collision TDES0 8 Excessive collision TDES0 2 Excessive deferral TDES0 1 Underflow error 14 JT Jabber timeout bit Only set when the JBD bit is reset 0 No jabber timeout occurred 1 The MAC transmitter has experienced a jabber timeout 13 FRMF Frame flushed bit This bit is set to flush the Tx frame by software 12 IPPE...

Page 695: ... frame bit 0 The transmitted frame was a normal frame 1 The transmitted frame was a VLAN type frame 6 3 COCNT 3 0 Collision count bits This 4 bit counter value indicates the number of collisions occurring before the frame was transmitted The count is not valid when the ECO bit TDES0 8 is set 2 EXD Excessive deferral bit This is valid when the DFC bit in the MAC configuration register is set 0 No e...

Page 696: ... the first data buffer If this field is 0 the TxDMA ignores this buffer and uses buffer 2 for TCHM 0 or the next descriptor for TCHM 1 TDES2 Transmit descriptor word 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TB1AP TTSL 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TB1AP TTSL 15 0 rw Bits Fields Descriptions 31 0 TB1AP TTSL 31 0 Transmit buffer 1 address pointer Transmit frame timestamp lo...

Page 697: ...itialize the receive descriptors with the DAV bit RXDES0 31 is set 2 Setting the SRE bit in ENET_DMA_CTL register to make RxDMA controller entering running state In running state the RxDMA controller continually fetching the receive descriptors from descriptor table whose starting address is configured in ENET_DMA_RDTADDR register by application If the DAV bit of the fetched receive descriptor is ...

Page 698: ... frame is greater than threshold in Cut Through mode or when the whole frame is received in Store and Forward mode Once exiting suspend mode the RxDMA controller fetches the next descriptor and the following operation goes to Step 2 Receive descriptor fetching regulation Descriptor fetching occurs if any one or more of the following conditions are met The time SRE bit is configured from 0 to 1 whi...

Page 699: ...or is set the RxDMA controller repeats above operation when received a new frame If the DAV bit of the next descriptor is reset the RxDMA controller enters suspend state and sets RBU bit in ENET_DMA_STAT register The pointer value of descriptor address table is retained and be used for the starting descriptor address after exiting suspend state Processing after a new frame received in suspend stat...

Page 700: ...escriptor The DMA clears this bit either when it completes the frame reception or when the buffers in this descriptor are full 0 The descriptor is owned by the CPU 1 The descriptor is owned by the DMA 30 DAFF Destination address filter fail bit 0 A frame passed the destination address filter 1 A frame failed the destination address filter 29 16 FRML 13 0 Frame length bits These bits indicate the b...

Page 701: ...the length field in received and the actual frame length 0 No length error occurred 1 Length error occurred 11 OERR Overflow error bit When RxFIFO is overflow and the frame data has been partly forwarded to descriptor buffer the overflow error bit sets 0 No overflow error occurred 1 RxFIFO overflowed and frame data is not valid 10 VTAG VLAN tag bit 0 Received frame is not a tag frame 1 Received fr...

Page 702: ...han 2048 bytes was detected When WDD 1 this bit indicates a frame with more than 16384 bytes was detected 0 No receive watchdog timeout occurred 1 Watchdog timer overflowed during receiving and current frame is only a part of frame 3 RERR Receive error bit This bit indicates the interface signal RX_ER asserted when RX_DV signal is active during frame receiving process 0 No receive error occurred 1...

Page 703: ...cksum error This error may cased by following condition 1 Calculated checksum value mismatch the checksum field 2 byte number of received payload mismatch length field 1 0 0 Reserved 1 0 1 A type length type field equal or greater than 0x0600 or tagged frame but neither IPv4 nor IPv6 Offload check engine is bypassed 1 1 0 IPv4 or IPv6 frame but an header checksum error detected This error may case...

Page 704: ...cond address bit 0 The second address points to the second buffer address 1 The second address points to the next descriptor address RB2S RDES1 28 16 is ignored Note If the RERM 1 the next descriptor returns to base address even this bit is set to 1 13 Reserved Must be kept at reset value 12 0 RB1S 12 0 Receive buffer 1 size bits The first buffer size in bytes The buffer size must be a multiple of...

Page 705: ...or by RxDMA controller these bits are configured to the buffer 2 address RCHM 0 or the next descriptor address RCHM 1 by application This buffer 2 address pointer is used for RxDMA controller to store the received frame if RB1S is not 0 when RCHM 0 If RCHM 1 and RERM 0 this address pointer is used for fetching the next descriptor If RCHM 1 and RERM 1 these bits are ignored When this address is use...

Page 706: ...ransmitting and receiving descriptors with DAV 1 and data buffer Enable MAC and DMA module to start transmit and receive Set TEN and REN bit in ENET_MAC_CFG register to make MAC work for transmit and receive Set STE and SRE bit in ENET_DMA_CTL register to make DMA controller work for transmit and receive If transmitting frames is needed 1 Choose one or more programmed transmitting descriptor write...

Page 707: ...This interrupt is inner mapped on the EXTI line 19 So if the EXTI line 19 is enabled and configured to trigger by rising edge the Ethernet WUM event can make the system exiting Deep sleep mode after a WUM event occurred In addition if the WUM interrupt is not masked both the EXTI line 19 interrupt and Ethernet normal interrupt to CPU are both generated Note Because of the WUM registers are designe...

Page 708: ...ts are cleared the corresponding summary interrupt bit is cleared If both normal and abnormal interrupts are cleared the DMA interrupt will be cleared Below block diagram illustrates the Ethernet module interrupt connection Figure 22 12 Ethernet interrupt scheme MSCI WUMI TMSTI Ethernet Interrupt AI AISE FBE FBEIE TPS TPSIE RO ROIE TJT TJTIE RBU RBUIE AND AND AND AND AND OR OR OR TU TUIE RWT RWTIE...

Page 709: ...23 WDD Watchdog disable bit This bit indicates the maximum bytes for receiving data beyond this will be cut off 0 The MAC allows no more than 2048 bytes of the frame being received 1 The MAC disables the watchdog timer on the receiver and can receive frames of up to 16384 bytes 22 JBD Jabber disable bit This bit indicates the maximum bytes for transmitting data data beyond this will be cut off 0 T...

Page 710: ...mode 1 The MAC operates in loopback mode at the MII 11 DPM Duplex mode bit 0 Half duplex mode enable 1 Full duplex mode enable 10 IPFCO IP frame checksum offload bit 0 The checksum offload function in the receiver is disabled 1 IP frame checksum offload function enabled for received IP frame 9 RTD Retry disable bit This bit is applicable only in the Half duplex mode 0 The MAC attempts retries up t...

Page 711: ... The MAC transmit function is disabled after finish the transmission of the current frame and no frames to be transmitted anymore 1 The transmit function of the MAC is enabled for transmission 2 REN Receiver enable bit 0 The MAC reception function is disabled after finish the reception of the current frame and no frames will be received anymore 1 The MAC reception function is enabled for receiving...

Page 712: ...se filtering bit This bit makes the result of SA matching inverse 0 Not inverse for source address filtering 1 Inverse source address filtering result When SA matches the enabled SA registers filter marks it as failing the SA address filter 7 6 PCFRM 1 0 Pass control frames bits These bits set the forwarding conditions for all control frames including unicast and multicast pause frame For pause co...

Page 713: ...is bit can make the filter bypassed which means all received frames are thought pass the filer and DA SA filtering result status in descriptor is always 0 0 Promiscuous mode disabled 1 Promiscuous mode enabled 22 4 3 MAC hash list high register ENET_MAC_HLH Address offset 0x0008 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HLH 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 714: ...eserved Must be kept at reset value 15 11 PA 4 0 PHY address bits These bits choose which PHY device is to be accessed 10 6 PR 4 0 PHY register bits These bits choose the register address in selected PHY device 5 Reserved Must be kept at reset value 4 2 CLR 2 0 Clock range bits MDC clock divided factor select which is decided by HCLK frequency range 0x0 HCLK 42 HCLK range 60 90 MHz 0x1 HCLK 64 HCL...

Page 715: ...Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 PD 15 0 PHY data bits For reading operation these bits contain the data from external PHY For writing operation these bits contain the data will be sent to external PHY 22 4 7 MAC flow control register ENET_MAC_FCTL Address offset 0x0018 Reset value 0x0000 0000 This register configures the generation and reception of the cont...

Page 716: ...ddress for pause frame which is specified in IEEE802 3 can be detected 1 Besides the unique multicast address MAC can also use the MAC0 address ENET_MAC_ADDR0H and ENET_MAC_ADDR0L register to detecting pause frame 2 RFCEN Receive flow control enable bit 0 Decode function for pause frame is disabled 1 Enable decoding function for the received pause frame and process it The MAC disables its transmit...

Page 717: ...low control This field configures the threshold of the deactive flow control The value should always be less than the Threshold of active flow control value configured in bits 2 0 When the value of the unprocessed data in RxFIFO is less than this value configured the flow control function will deactive 0x0 256 bytes 0x1 512 bytes 0x2 768 bytes 0x3 1024 bytes 0x4 1280 bytes 0x5 1536 bytes 0x6 0x7 1...

Page 718: ...omparison 0 All 16 bits the 15th and 16th byte of the VLAN tag in received frame are used for comparison 1 Only low 12 bits of the VLAN tag in received frame are used for comparison 15 0 VLTI 15 0 VLAN tag identifier for receive frames bits These bits are configured for detecting VLAN frame using 802 1Q VLAN tag format The format shows below VLTI 15 13 UP user priority VLTI 12 CFI canonical format...

Page 719: ...reg2 Wakeup frame filter reg3 Wakeup frame filter reg4 Wakeup frame filter reg5 Wakeup frame filter reg6 Wakeup frame filter reg7 31 0 Wakeup frame filter reg0 22 4 11 MAC wakeup management register ENET_MAC_WUM Address offset 0x002C Reset value 0x0000 0000 This register configures the request of wakeup events and monitors the wakeup events 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WUFFRPR R...

Page 720: ...n 1 MPEN Magic Packet enable bit 0 Disable generating a wakeup event due to Magic Packet reception 1 Enable generating a wakeup event due to Magic Packet reception 0 PWD Power down bit This bit is set by application and reset by hardware When this bit is set MAC drops all received frames When power down mode exit because of wakeup event occurred hardware resets this bit 22 4 12 MAC interrupt flag ...

Page 721: ...y of bit 6 MSCT or bit 5 MSCR is set high 3 WUM WUM status bit This bit is logic ORed from WUFR and MPKR bit in ENET_MAC_WUM register 0 Wakeup frame or Magic Packet frame is not received 1 A Magic packet or remote wakeup frame is received in power down Mode 2 0 Reserved Must be kept at reset value 22 4 13 MAC interrupt mask register ENET_MAC_INTMSK Address offset 0x003C Reset value 0x0000 0000 31 ...

Page 722: ...1 MO Always read 1 and must be kept 30 16 Reserved Must be kept at reset value 15 0 ADDR0H 15 0 MAC address0 high16 bit These bits contain the high 16 bit bit 47 to 32 of the 6 byte MAC address0 These bits are used for address filtering in frame reception and address inserting in pause frame transmitting during transmit flow control 22 4 15 MAC address 0 low register ENET_MAC_ADDR0L Address offset...

Page 723: ...for perfect filtering 30 SAF Source address filter bit 0 The MAC address1 47 0 is used to comparing with the DA field of the received frame 1 The MAC address1 47 0 is used to comparing with the SA field of the received frame 29 24 MB 5 0 Mask byte bits When they are set high the MAC does not compare the corresponding byte of received DA SA with the contents of the MAC address1 registers Each bit c...

Page 724: ...1 20 19 18 17 16 AFE SAF MB 5 0 Reserved rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR2H 15 0 rw Bits Fields Descriptions 31 AFE Address filter enable bit 0 The address filter ignores the MAC address2 for filtering 1 The address filter uses the MAC address2 for perfect filtering 30 SAF Source address filter bit 0 The MAC address2 47 0 is used to comparing with the DA fields of the received f...

Page 725: ...eset value 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR2L 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR2L 15 0 rw Bits Fields Descriptions 31 0 ADDR2L 31 0 MAC address2 low 32 bit This field contains the low 32 bit of the 6 byte MAC address2 22 4 20 MAC address 3 high register ENET_MAC_ADDR3H Address offset 0x0058 Reset value 0x0000 FFFF 31 30 29 28 27 26 25 24 23 22 21 2...

Page 726: ...15 8 MB 4 ENET_MAC_ADDR3H 7 0 MB 3 ENET_MAC_ADDR3L 31 24 MB 2 ENET_MAC_ADDR3L 23 16 MB 1 ENET_MAC_ADDR3L 15 8 MB 0 ENET_MAC_ADDR3L 7 0 23 16 Reserved Must be kept at reset value 15 0 ADDR3H 15 0 MAC address3 high 16 bit This field contains the high 16 bit bit 47 to 32 of the 6 byte MAC address3 22 4 21 MAC address 3 low register ENET_MAC_ADDR3L Address offset 0x005C Reset value 0xFFFF FFFF 31 30 2...

Page 727: ...re reset to zero after read them 1 CTSR Counter stop rollover bit 0 The counters roll over to zero after they reached the maximum value 1 The counters do not roll over to zero after they reached the maximum value 0 CTR Counter reset bit Cleared by hardware 1 clock after set This bit is cleared automatically after 1 clock cycle 0 No effect 1 Reset all counters 22 4 23 MSC receive interrupt flag reg...

Page 728: ...108 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TGF Reserved rc_r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TGFMSC TGFSC Reserved rc_r rc_r Bits Fields Descriptions 31 22 Reserved Must be kept at reset value 21 TGF Transmitted good frames bit 0 Good frame transmitted counter is less than half of the maximum value 1 Good frame transmitted counter reaches half of the...

Page 729: ...ed good unicast frames interrupt mask bit 0 Unmask the interrupt when the RGUF bit is set 1 Mask the interrupt when RGUF bit is set 16 7 Reserved Must be kept at reset value 6 RFAEIM Received frames alignment error interrupt mask bit 0 Unmask the interrupt when the RFAE bit is set 1 Mask the interrupt when the RFAE bit is set 5 RFCEIM Received frame CRC error interrupt mask bit 0 Unmask the interr...

Page 730: ...GFSCIM Transmitted good frames single collision interrupt mask bit 0 Unmask the interrupt when the TFGSC bit is set 1 Mask the interrupt when the TFGSC bit is set 13 0 Reserved Must be kept at reset value 22 4 27 MSC transmitted good frames after a single collision counter register ENET_MSC_SCCNT Address offset 0x014C Reset value 0x0000 0000 This register counts the number of successfully transmit...

Page 731: ...5 0 r Bits Fields Descriptions 31 0 MSCC 31 0 Transmitted good frames more one single collision counter bits These bits count the number of a transmitted good frames after more than one single collision 22 4 29 MSC transmitted good frames counter register ENET_MSC_TGFCNT Address offset 0x0168 Reset value 0x0000 0000 This register counts the number of good frames transmitted 31 30 29 28 27 26 25 24...

Page 732: ...eceived frames with CRC error counter bits These bits count the number of receive frames with CRC error 22 4 31 MSC received frames with alignment error counter register ENET_MSC_RFAECNT Address offset 0x0198 Reset value 0x0000 0000 This register counts the number of received frames with alignment error 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RFAER 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 733: ...NET_PTP_TSCTL Address offset 0x0700 Reset value 0x0000 0000 This register configures the generation and updating for timestamp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TMSARU TMSITEN TMSSTU TMSSTI TMSFCU TMSEN rw rw rw rw rw rw Bits Fields Descriptions 31 6 Reserved Must be kept at reset value 5 TMSARU Time stamp addend register update...

Page 734: ...d without any change 1 Initializing the system time with the value in timestamp update high and low registers It is cleared by hardware when the initialization finished 1 TMSFCU Timestamp fine or coarse update bit 0 The system timestamp uses the coarse method for updating 1 The system timestamp uses the fine method for updating 0 TMSEN Timestamp enable bit 0 Disable timestamp function 1 Enable tim...

Page 735: ... 5 4 3 2 1 0 STMS 15 0 r Bits Fields Descriptions 31 0 STMS 31 0 System time second bits These bits show the current second of the system time 22 4 36 PTP time stamp low register ENET_PTP_TSL Address offset 0x070C Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 STS STMSS 30 16 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STMSS 15 0 r Bits Fields Descriptions 31 STS System time...

Page 736: ...2 1 0 TMSUS 15 0 rw Bits Fields Descriptions 31 0 TMSUS 31 0 Time stamp update second bits These bits are used for initializing or adding subtracting to second of the system time 22 4 38 PTP time stamp update low register ENET_PTP_TSUL Address offset 0x0714 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TMSUPNS TMSUSS 30 16 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMSUS...

Page 737: ... 15 0 rw Bits Fields Descriptions 31 0 TMSA 31 0 Time stamp addend bits These registers contain a 32 bit time value which is added to the accumulator register to achieve time synchronization 22 4 40 PTP expected time high register ENET_PTP_ETH Address offset 0x071C Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ETSH 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETSH 15 0 ...

Page 738: ...aligned bit 0 Disable address aligned 1 Enabled address aligned If the FB 1 all AHB interface address is aligned to the start address LS bits bit 1 to 0 If the FB 0 the AHB interface first access address accessing the data buffer s start address is not aligned but subsequent burst access addresses are aligned to the address 24 FPBL Four times PGBL mode bit 0 The PGBL value programmed bits 22 17 an...

Page 739: ... RxDMA TxDMA 2 1 0x2 RxDMA TxDMA 3 1 0x3 RxDMA TxDMA 4 1 Note This bit is valid only when the arbitration mode is Round robin DAB 0 13 8 PGBL 5 0 Programmable burst length bits These bits indicate the maximum number of beats to be transferred in one DMA transaction When UIP 1 the PGBL value is only used for TxDMA When UIP 0 the PGBL value is used for both TxDMA and RxDMA 0x01 max beat number is 1 ...

Page 740: ...ontroller poll the transmit descriptor table The TxDMA controller can go into suspend state because of an underflow error in a transmitted frame or the descriptor unavailable DAV 0 Application can write any value into this register for attempting to re fetch the current descriptor 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TPE 31 16 rw_wt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPE 15 0 rw_wt B...

Page 741: ...navailable DAV 0 the DMA returns to suspend state again and the RBU bit in ENET_DMA_STAT register will be set 22 4 45 DMA receive descriptor table address register ENET_DMA_RDTADDR Address offset 0x100C Reset value 0x0000 0000 This register points to the start of the receive descriptor table The descriptor table is located in the physical memory space and must be word aligned This register can onl...

Page 742: ...the start address of the transmit descriptor table STT 1 0 are internally taken as zero so STT 1 0 are read only 22 4 47 DMA status register ENET_DMA_STAT Address offset 0x1014 Reset value 0x0000 0000 This register contains all the status bits that the DMA controller recorded Writing 1 to meaningful bits in this register clears them but writing 0 has no effect Each bit bits 16 0 can be masked by m...

Page 743: ...vent has occurred 26 Reserved Must be kept at reset value 25 23 EB 2 0 Error bits status bit When FBE 1 these bits decode the type of error that caused a bus response error on AHB bus EB 0 1 Error during data transfer by TxDMA 0 Error during data transfer by RxDMA EB 1 1 Error during read transfer 0 Error during write transfer EB 2 1 Error during descriptor access 0 Error during data buffer access...

Page 744: ...lowing if the corresponding interrupt bit is enabled in the ENET_DMA_INTEN register TPS ENET_DMA_STAT 1 Transmit process stopped TJT ENET_DMA_STAT 3 Transmit jabber timeout RO ENET_DMA_STAT 4 Receive FIFO overflow TU ENET_DMA_STAT 5 Transmit underflow RBU ENET_DMA_STAT 7 Receive buffer unavailable RPS ENET_DMA_STAT 8 Receive process stopped RWT ENET_DMA_STAT 9 Receive watchdog timeout ET ENET_DMA_...

Page 745: ...low status bit 0 Underflow error has not occurred during frame transmission 1 The TxFIFO encountered an underflow error during frame transmission and entered suspend state 4 RO Receive overflow status bit 0 Receive overflow error has not occurred during frame reception 1 The RxFIFO encountered an overflow error during frame reception If a part of frame data has transferred to the memory the overfl...

Page 746: ...r frames disable bit 0 All error frames will be dropped when FERF 0 1 The received frame with only payload error but no other errors will not be dropped 25 RSFD Receive Store and Forward bit 0 The RxFIFO operates in Cut Through mode The forwarding threshold depends on the RTHC bits 1 The RxFIFO operates in Store and Forward mode The RTHC bits are don t care and the frame forwarding starts after th...

Page 747: ...ss pointer If the TxDMA controller is in suspend state reset this bit make the controller entering stop state 1 The TxDMA controller will enter running state TxDMA controller fetches current descriptor address for frame transmitting Transmit descriptor s fetching can either from base address in ENET_DMA_TDTADDR register or from the pointer position when transmission was stopped previously If the D...

Page 748: ...me data into TxFIFO but before the status of the first frame is written back to descriptor 1 SRE Start stop receive enable bit 0 The RxDMA controller will enter stop state after transfer complete if current received frame is transmitting to memory by RxDMA After transfer complete the next descriptor address in the receive table will become the current descriptor address when restart the RxDMA cont...

Page 749: ...TAT 0 Transmit interrupt TBU ENET_DMA_STAT 2 Transmit buffer unavailable RS ENET_DMA_STAT 6 Receive interrupt ER ENET_DMA_STAT 14 Early receive interrupt 15 AIE Abnormal interrupt summary enable bit 0 An abnormal interrupt is disabled 1 An abnormal interrupt is enabled This bit enables the following bits TPS ENET_DMA_STAT 1 Transmit process stopped TJT ENET_DMA_STAT 3 Transmit jabber timeout RO EN...

Page 750: ...rrupt is enabled 6 RIE Receive interrupt enable bit 0 The receive interrupt is disabled 1 The receive interrupt is disabled 5 TUIE Transmit underflow interrupt enable bit 0 The underflow interrupt is disabled 1 The underflow interrupt is enabled 4 ROIE Receive overflow interrupt enable bit 0 The overflow interrupt is disabled 1 The overflow interrupt is enabled 3 TJTIE Transmit jabber timeout inte...

Page 751: ... bit for FIFO overflow counter bit Overflow bit for FIFO overflow counter 27 17 MSFA 10 0 Missed frames by the application bits These bits indicate the number of frames dropped by RxFIFO 16 OBMFC Overflow bit for missed frame counter 15 0 MSFC 15 0 Missed frames by the controller bits These bits indicate the number of frames missed by the RxDMA controller because of the unavailable receive buffer ...

Page 752: ... address of the current receive descriptor read by the RxDMA controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDAP 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDAP 15 0 r Bits Fields Descriptions 31 0 RDAP 31 0 Receive descriptor address pointer bits These bits are automatically updated by RxDMA controller during operation 22 4 53 DMA current transmit buffer address register ENET_DMA_C...

Page 753: ...eceive buffer address register ENET_DMA_CRBADDR Address offset 0x1054 Reset value 0x0000 0000 This register points to the current receive buffer address being read by the RxDMA controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RBAP 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RBAP 15 0 r Bits Fields Descriptions 31 0 RBAP 31 0 Receive buffer address pointer bits These bits are automatica...

Page 754: ...tocol 23 2 Characteristics USB 2 0 full speed device controller Support up to 8 configurable bidirectional endpoints Support double buffered bulk isochronous endpoints Each endpoint supports control bulk isochronous or interrupt transfer types exclude endpoint 0 endpoint 0 only support control transfe Support USB suspend resume operations Shared dedicated 512 byte SRAM used for data packet buffer ...

Page 755: ...buffer overflow and underflow 48MHz clock of USB controller can be generated by dividing MCU internal or external crystal oscillator by a programmable prescaler then multiplicating the frequency through PLL Regard two frequency division of 8MHz internal oscillator as the input of the PLL then 12 frequencies doubling the clock Regard 8MHz external oscillator as the input of the PLL firstly frequenc...

Page 756: ... data payload The bidirectional endpoint has usually two buffers one is used for transmission and the other one is for reception The mono directional endpoint only has one buffer for data operation Note The USBD and CAN share the dedicated 512 byte SRAM memory Endpoint buffer descriptor table USBD implements an endpoint buffer descriptor table which defines the buffer address and length and which ...

Page 757: ...ndpoints The double buffered feature is used to improve bulk transfer performance To implement the new flow control scheme the USB peripheral should know which packet buffer is currently in use by the application software so to be aware of any conflict Since in the USBD_EPxCS register there are two data toggle bits TX_DTG and RX_DTG but only one is used by USBD for hardware data handling due to th...

Page 758: ...RBCNT buffer description table locations IN 0 1 EPxTBADDR EPxTBCNT buffer description table locations EPxRBADDR EPxRBCNT buffer description table locations 1 0 EPxRBADDR EPxRBCNT buffer description table locations EPxTBADDR EPxTBCNT buffer description table locations Endpoint memory requests arbitration As the USBD is connected to the APB1 bus through an APB1 interface so USB APB1 interface will a...

Page 759: ...ll the data packet memory with data start next transfer by re enable the endpoint by setting the endpoint status VALID OUT and SETUP transaction USBD handles these two tokens more or less in the same way the differences in the handling of SETUP packets will be detailed in the following section about control transfer After the received endpoint is configured and enabled host will send OUT SETUP tok...

Page 760: ... and is required to set the unused direction endpoint 0 status to STALL except the last data stage At the last data stage the application software set the opposite direction endpoint 0 status to NAK This will keep the host waiting for the completion of the control operation If the operation completes successfully the software will change NAK to VALID otherwise to STALL If the status stage is an OU...

Page 761: ...interrupts and events Reset events System and power on reset Upon system and power on reset the application software should first provide all required clock to the USB module and interface then de assert its reset signal so to be able to access its registers last switch on the analog part of the device related to the USB transceiver The USB firmware should do as follows Reset CLOSE bit in USBD_CTL...

Page 762: ...eption Setting the LOWM bit to 1 will shut down the static power consumption in the analog USB transceivers but the RESUME signal is still able to be detected USB Interrupts USBD has three interrupts low priority interrupt high priority interrupt and wakeup interrupt Software can configure these interrupts to route the interrupt condition to these entries in the NVIC table An interrupt will be gen...

Page 763: ...er but both of them are set to 10 NAK if use endpoint 0 to initialize the control transfer If the endpoint is a double buffer endpoint 1 Both transmission and reception toggle fields need to be programmed If the endpoint is a Tx endpoint clear the TX_DTG and RX_DTG bit in USBD_EPxCS register or if endpoint is a Rx endpoint it needs to toggle TX_DTG bit 2 Program USBD_EPxTBCNT and USBD_EPxRBCNT reg...

Page 764: ...D_EPxTBCNT register to set EPTXCNT filed this filed defines the endpoint buffer length 2 Configure the endpoint status to be VALID to enable the endpoint to transmit data by programming USBD_EPxCS register 3 Wait for successful transfer interrupt STIF 4 In the interrupt handler application needs to update user buffer length and location pointer Then application fill the endpoint buffer with user b...

Page 765: ...ket memory overrun underrun 1 Interrupt generated when PMOUIF bit in USBD_INTF register is set 13 ERRIE Error interrupt enable 0 Error interrupt disabled 1 Interrupt generated when ERRIF bit in USBD_INTF register is set 12 WKUPIE Wakeup interrupt enable 0 Wakeup interrupt disabled 1 Interrupt generated when WKUPIF bit in USBD_INTF register is set 11 SPSIE Suspend state interrupt enable 0 Suspend s...

Page 766: ...te If resume from suspend state the hardware reset this bit 0 No effect 1 Go to low power mode at suspend state 1 CLOSE Close state When this bit is set the USBD goes to close state and completely close the USBD and disconnected from the host 0 Not in close state 1 In close state 0 SETRST Set reset When this bit is set the USBD peripheral should be reset 0 No reset 1 A reset generated 23 7 2 USBD ...

Page 767: ... bit 10 RSTIF USB reset interrupt flag Set by hardware when the USB RESET signal is detected The software writes 0 to clear this bit 9 SOFIF Start of frame interrupt flag Set by hardware when a new SOF packet arrives The software writes 0 to clear this bit 8 ESOFIF Expected start of frame interrupt flag Set by the hardware to indicate that a SOF packet is expected but not received The software wri...

Page 768: ...ted every SOF received 23 7 4 USBD device address register USBD_DADDR Address offset 0x4C Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved USBEN USBDAR 6 0 rw rw Bits Fields Descriptions 15 8 Reserved Must be kept at reset value 7 USBEN USB device enable Set by software to enable the USB device 0 The USB device disab...

Page 769: ...0 RX_ST RX_DTG RX_STA 1 0 SETUP EP_CTL 1 0 EP_KCTL TX_ST TX_DTG TX_STA 1 0 EP_ADDR 3 0 rc_w0 t t r rw rw rc_w0 t t rw Bits Fields Descriptions 15 RX_ST Reception successful transferred Set by hardware when a successful OUT SETUP transaction complete Cleared by software by writing 0 14 RX_DTG Reception data PID toggle This bit represent the toggle data bit 0 DATA0 1 DATA1 for non isochronous endpoi...

Page 770: ... Endpoint address Used to direct the transaction to the target endpoint Table 23 4 Reception status encoding RX_STA 1 0 Meaning 00 DISABLED ignore all reception requests of this endpoint 01 STALL STALL handshake status 10 NAK NAK handshake status 11 VALID enable endpoint for reception Table 23 5 Endpoint type encoding EP_CTL 1 0 Meaning 00 BULK bulk endpoint 01 CONTROL control endpoint 10 ISO isoc...

Page 771: ...ceive next IN token 0 EPTXBAR 0 Must be set to 0 23 7 8 USBD endpoint x transmission buffer byte count register USBD_EPxTBCNT x can be in 0 7 Address offset USBD_BADDR x 16 4 USB local Address USBD_BADDR x 8 2 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EPTXCNT 9 0 rw Bits Fields Descriptions 15 10 Reserved Must be kept at reset v...

Page 772: ...USBD endpoint x reception buffer byte count register USBD_EPxRBCNT x can be in 0 7 Address offset USBD_BADDR x 16 12 USB local Address USBD_BADDR x 8 6 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BLKSIZ BLKNUM 4 0 EPRCNT 9 0 rw rw r Bits Fields Descriptions 15 BLKSIZ Block size 0 block size is 2 bytes 1 block size is 32 bytes 14 10 BLKNUM ...

Page 773: ...TG protocol with HNP Host Negotiation Protocol and SRP Session Request Protocol Supports all the 4 types of transfer control bulk interrupt and isochronous Includes a USB transaction scheduler in host mode to handle USB transaction request efficiently Includes a 1 25KB FIFO RAM Supports 8 channels in host mode Includes 2 transmit FIFOs periodic and non periodic and a receive FIFO shared by all cha...

Page 774: ...nd working modes USBFS could be operated as a host a device or a DRD Dual Role Device It contains an internal full speed PHY The maximum speed supported by USBFS is full speed The internal PHY supports Full Speed and Low Speed in host mode supports Full speed in device mode and supports OTG mode with HNP and SRP The USB clock used by the USBFS should be 48MHz The 48MHz USB clock is generated from ...

Page 775: ...is cleared and FDM bit is set the VBUS detection circuit is connected to a GPIO pin USBFS continuously monitor the VBUS voltage by the GPIO pin and will immediately switch on the pull up resistor on DP line once that the VBUS voltage rise above the needed valid value This will cause a connection If the VBUS voltage falls below the needed valid value the pull up resistor on DP line will be switched...

Page 776: ...tate After PP bit is set by software the internal USB PHY is powered on and the USB port changes into disconnected state After a connection is detected USB port changes into connected state The USB port changes into enabled state after a port reset is performed on USB bus Figure 24 4 State transition diagram of host port Power off Dis connected Connected Enabled set PP bit clear PP bit or VBUS is ...

Page 777: ...equence The WKUPIF bit in USBFS_GINTF will be set and then the USBFS wake up interrupt will be triggered if a host in suspend state detects a remote wakeup signal SOF generate USBFS sends SOF tokens on USB bus in host mode As describing in USB 2 0 protocol SOF packets are generated by the host controller or hub transaction translator at each 1ms in full speed links Once that USBFS enterred into en...

Page 778: ... Each time the USBFS reads and pops a request entry from request queue If this is a channel disable request it immediately disables the channel and prepares to process the next entry If the current request is a transaction request and the USB bus time is enough for this transaction USBFS will employ SIE to generate this transaction on USB bus When the required bus time for the current request is n...

Page 779: ...witch off the pull up resistor so that USB host will detect a disconnection on USB bus SOF tracking When USBFS receives a SOF packet on USB bus it will trigger a SOF interrupt and begin to count the bus time by using local USB clock The frame number of the current frame is reported in FNRSOF filed in USBFS_DSTAT register When the USB bus time reaches EOF1 or EOF2 point End of Frame described in US...

Page 780: ...t and the USBFS will begin to perform HNP protocol on bus and at last the result of HNP is reported in HNPS bit in USBFS_GOTGCS register In additional it is always available to get the current role host or device from COPM bit in USBFS_GINTF register SRP The Session Request Protocol SRP allows a B Device to request the A Device to turn on VBUS and start a session This protocol allows the A Device ...

Page 781: ...ter map describes the register memory area that the data FIFO can access The addresses in the figure are addressed in bytes Each channel has its own FIFO access register space although all Non periodic channels share the same FIFO and all the Periodic channels also share the same FIFO It is important for USBFS to know which channel the current pushed packet belongs to Rx FIFO is also able to be ac...

Page 782: ...eading and writing Figure 24 8 Device mode FIFO access register map describes the register memory area where the data FIFO can access The addresses in the figure are addressed in bytes Each endpoint has its own FIFO access register space Rx FIFO is also able to be accessed by using USBFS_GRSTATR USBFS_GRSTATP register Figure 24 8 Device mode FIFO access register map IEP0 FIFO Write IEP1 FIFO Write...

Page 783: ...ait for at least 10ms and then clear PRST bit 8 Wait PEDC interrupt in USBFS_HPCS register and then read PE bit to ensure that the port is successfully enabled Read PS 1 0 bits to get the connected device s speed and then program USBFS_HFT register to change the SOF interval if needed Channel initialization and enable sequence 1 Program USBFS_HCHxCTL registers with desired transfer type direction ...

Page 784: ...rresponding request queue 5 When the Rx request entry reaches the top of the request queue USBFS begins to process this request entry If bus time for the IN transaction indicated by the request entry is enough USBFS starts the IN transaction on USB bus 6 If the IN transaction is finished successfully ACK handshake received USBFS pushes the received data packet into the Rx FIFO and triggers ACK fla...

Page 785: ...ful return to step 3 to resend the packet again 7 After all the transactions in a transfer are successfully sent on USB bus USBFS generates TF flag to indicate that the transfer successfully finishes 8 Disable the channel Now the channel is in IDLE state and is ready for other transfers Device mode Global register initialization sequence 1 Program USBFS_GAHBCS register according to application s d...

Page 786: ...ved data size before the OUT transaction finishes TLEN can be set to a maximum possible value supported by Rx FIFO 4 Set EPEN bit in USBFS_DIEPxCTL or USBFS_DOEPxCTL register to enable the endpoint Endpoint disable sequence The endpoint could be disabled anytime when the EPEN bit in USBFS_DIEPxCTL or USBFS_DOEPxCTL registers is cleared IN transfers operation sequence 1 Initialize USBFS global regi...

Page 787: ...r successfully is finished and the OUT endpoint is disabled 24 6 Interrupts USBFS has two interrupts global interrupt and wake up interrupt The source flags of the global interrupt are readable in USBFS_GINTF register and are listed in Table 24 2 USBFS global interrupt Table 24 2 USBFS global interrupt Interrupt Flag Description Operation Mode SESIF Session interrupt Host or device mode DISCIF Dis...

Page 788: ... mode NPTXFEIF Non Periodic Tx FIFO empty interrupt flag Host Mode RXFNEIF Rx FIFO non empty interrupt flag Host or device mode SOF Start of frame Host or device mode OTGIF OTG interrupt flag Host or device mode MFIF Mode fault interrupt flag Host or device mode Wake up interrupt can be triggered when USBFS is in suspend state even if when the USBFS s clocks are stopped The source of the wake up i...

Page 789: ...ions 31 20 Reserved Must be kept at reset value 19 BSV B Session Valid described in OTG protocol 0 Vbus voltage level of a OTG B Device is below VBSESSVLD 1 Vbus voltage level of a OTG B Device is not below VBSESSVLD Note Only accessible in OTG B Device mode 18 ASV A Session valid A host mode transceiver status 0 Vbus voltage level of a OTG A Device is below VASESSVLD 1 Vbus voltage level of a OTG...

Page 790: ...leared USBFS doesn t response to the HNP request from B Device 0 HNP function is not enabled 1 HNP function is enabled Note Only accessible in host mode 9 HNPREQ HNP request This bit is set by software to start a HNP on the USB This bit can be cleared when HNPEND bit in USBFS_GOTGINTF register is set by writing zero to it or clearing the HNPEND bit in USBFS_GOTGINTF register 0 Don t send HNP reque...

Page 791: ...21 20 19 18 17 16 Reserved DF ADTO HNPDET Reserved rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved HNPEND SRPEND Reserved SESEND Reserved rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31 20 Reserved Must be kept at reset value 19 DF Debounce finish Set by USBFS when the debounce during device connection is done Note Only accessible in host mode 18 ADTO A Device timeout Set by USBFS w...

Page 792: ... voltage is below Vb_ses_vld 1 0 Reserved Must be kept at reset value Global AHB control and status register USBFS_GAHBCS Address offset 0x0008 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PTXFTH TXFTH Reserved GINTEN rw rw rw Bits Fields Descriptions 31 9 Reserved Mus...

Page 793: ...ssible in both device and host modes Global USB control and status register USBFS_GUSBCS Address offset 0x000C Reset value 0x0000 0A80 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FDM FHM Reserved rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UTT 3 0 HNPCEN SRPCEN Reserved TOC 2 0 rw r rw r rw rw Bits Fields Descriptions 31 Reserve...

Page 794: ...is enabled Note Accessible in both device and host modes 8 SRPCEN SRP capability enable Controls whether the SRP capability is enabled 0 SRP capability is disabled 1 SRP capability is enabled Note Accessible in both device and host modes 7 3 Reserved Must be kept at reset value 2 0 TOC 2 0 Timeout calibration USBFS always uses time out value required in USB 2 0 when waiting for a packet Applicatio...

Page 795: ...ts decide the FIFO number to be flushed Hardware automatically clears this bit after the flush process completes After setting this bit application should wait until this bit is cleared before any other operation on USBFS Note Accessible in both device and host modes 4 RXFF Rx FIFO flush Application set this bit to flush data Rx FIFO Hardware automatically clears this bit after the flush process c...

Page 796: ...DPSC Reserved PTXFEIF HCIF HPIF Reserved PXNCIF ISOONCIF ISOINCIF OEPIF IEPIF Reserved rc_w1 rc_w1 rc_w1 rc_w1 r r r rc_w1 rc_w1 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EOPFIF ISOOPDIF ENUMF RST SP ESP Reserved GONAK GNPINAK NPTXFEIF RXFNEIF SOF OTGIF MFIF COPM rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 r r r r rc_w1 r rc_w1 r Bits Fields Descriptions 31 WKUPIF Wakeup interrupt flag This interrupt is t...

Page 797: ...ort status changes in host mode Software should read USBFS_HPCS register to get the source of this interrupt This bit will be automatically cleared after the flags that causing a port interrupt are cleared Note Only accessible in host mode 23 22 Reserved Must be kept at reset value 21 PXNCIF ISOONCIF Periodic transfer Not Complete Interrupt flag USBFS sets this bit when there are periodic transact...

Page 798: ...fined by EOPFT 1 0 bits in USBFS_DCFG register USBFS sets this flag Note Only accessible in device mode 14 ISOOPDIF Isochronous OUT packet dropped interrupt flag USBFS set this bit if it receives an isochronous OUT packet but cannot save it into Rx FIFO because the FIFO doesn t have enough space Note Only accessible in device mode 13 ENUMF Enumeration finished USBFS sets this bit after the speed e...

Page 799: ... USB bus Software can clear this bit by writing 1 Device Mode USBFS sets this bit after it receives a SOF token The application can read the Device Status register to get the current frame number Software can clear this bit by writing 1 Note Accessible in both host and device modes 2 OTGIF OTG interrupt flag USBFS sets this bit when the flags in USBFS_GOTGINTF register generate an interrupt Softwa...

Page 800: ...IE OTGIE MFIE Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 WKUPIE Wakeup interrupt enable 0 Disable wakeup interrupt 1 Enable wakeup interrupt Note Accessible in both host and device modes 30 SESIE Session interrupt enable 0 Disable session interrupt 1 Enable session interrupt Note Accessible in both host and device modes 29 DISCIE Disconnect interrupt enable 0 Disab...

Page 801: ...t Note Only accessible in device mode 20 ISOINCIE Isochronous IN transfer not complete interrupt enable 0 Disable isochronous IN transfer not complete interrupt 1 Enable isochronous IN transfer not complete interrupt Note Only accessible in device mode 19 OEPIE OUT endpoints interrupt enable 0 Disable OUT endpoints interrupt 1 Enable OUT endpoints interrupt Note Only accessible in device mode 18 I...

Page 802: ...set value 7 GONAKIE Global OUT NAK effective interrupt enable 0 Disable global OUT NAK interrupt 1 Enable global OUT NAK interrupt Note Only accessible in device mode 6 GNPINAKIE Global non periodic IN NAK effective interrupt enable 0 Disable global non periodic IN NAK effective interrupt 1 Enable global non periodic IN NAK effective interrupt Note Only accessible in device mode 5 NPTXFEIE Non per...

Page 803: ... Reset value 0x0000 0000 A read to the receive status read register returns the entry of the top of the Rx FIFO A read to the Receive status read and pop register additionally pops the top entry out of the Rx FIFO The entries in RxFIFO have different meanings in host and device modes Software should only read this register after when Receive FIFO non empty interrupt flag bit of the global interrup...

Page 804: ...NUM 3 0 Channel number The channel number to which the current received packet belongs Device mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RPCKST 3 0 DPID r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DPID BCOUNT 10 0 EPNUM 3 0 r r r Bits Fields Descriptions 31 21 Reserved Must be kept at reset value 20 17 RPCKST 3 0 Received packet status 0001 Global OUT NAK generates an interrupt 00...

Page 805: ...has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXFD 15 0 r rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 RXFD 15 0 Rx FIFO depth In terms of 32 bit words 1 RXFD 1024 Host non periodic transmit FIFO length register Device IN endpoint 0 transmit FIFO length USBFS_HNPTFLEN _DIEP0TFLEN Addre...

Page 806: ...ndpoint 0 Tx FIFO depth In terms of 32 bit words 16 IEP0TXFD 140 15 0 IEP0TXRSAR 15 0 IN Endpoint 0 TX RAM start address The start address for endpoint0 transmit FIFO RAM is in term of 32 bit words Host non periodic transmit FIFO queue status register USBFS_HNPTFQSTAT Address offset 0x002C Reset value 0x0008 0200 This register reports the current status of the non periodic Tx FIFO and request queu...

Page 807: ...ndicating last entry for selected channel 23 16 NPTXRQS 7 0 Non periodic Tx request queue space The remaining space of the non periodic transmit request queue 0 Request queue is Full 1 1 entry 2 2 entries n n entries 0 n 8 Others Reserved 15 0 NPTXFS 15 0 Non periodic Tx FIFO space The remaining space of the non periodic transmit FIFO In terms of 32 bit words 0 Non periodic Tx FIFO is full 1 1 wor...

Page 808: ...0 VBUS B device comparer disabled 1 VBUS B device comparer enabled 18 VBUSACEN The VBUS A device Comparer enable 0 VBUS A device comparer disabled 1 VBUS A device comparer enabled 17 Reserved Must be kept at reset value 16 PWRON Power on This bit is the power switch for the internal embedded Full Speed PHY 0 Embedded Full Speed PHY power off 1 Embedded Full Speed PHY power on 15 0 Reserved Must be...

Page 809: ...FIFO length register USBFS_HPTFLEN Address offset 0x0100 Reset value 0x0200 0600 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HPTXFD 15 0 r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HPTXFSAR 15 0 r rw Bits Fields Descriptions 31 16 HPTXFD 15 0 Host Periodic Tx FIFO depth In terms of 32 bit words 1 HPTXFD 1024 15 0 HPTXFSAR 15 0 Host periodic Tx FIF...

Page 810: ...Fields Descriptions 31 16 IEPTXFD 15 0 IN endpoint Tx FIFO depth In terms of 32 bit words 1 HPTXFD 1024 15 0 IEPTXRSAR 15 0 IN endpoint FIFO Tx RAM start address The start address for IN endpoint transmit FIFOx is in term of 32 bit words 24 7 2 Host control and status registers Host control register USBFS_HCTL Address offset 0x0400 Reset value 0x0000 0000 This register configures the core after po...

Page 811: ...controller is enumerating This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FRI 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 FRI 15 0 Frame interval This value describes the frame time in terms of PHY clocks Each time when port is enabled after a port reset operation USB...

Page 812: ...me of current frame in terms of PHY clocks 15 0 FRNUM 15 0 Frame number This field reports the frame number of current frame and returns to 0 after it reaches 0x3FFF Host periodic transmit FIFO queue status register USBFS_HPTFQSTAT Address offset 0x0410 Reset value 0x0008 0200 This register reports the current status of the host periodic Tx FIFO and request queue The request queue holds IN OUT or ...

Page 813: ...queue 0 Request queue is Full 1 1 entry 2 2 entries n n entries 0 n 8 Others Reserved 15 0 PTXFS 15 0 Periodic Tx FIFO space The remaining space of the periodic transmit FIFO In terms of 32 bit words 0 periodic Tx FIFO is full 1 1 word 2 2 words n n words 0 n PTXFD Others Reserved Host all channels interrupt register USBFS_HACHINT Address offset 0x0414 Reset value 0x0000 0000 When a channel interr...

Page 814: ...0x0418 Reset value 0x0000 0000 This register can be used by software to enable or disable a channel s interrupt Only the channel whose corresponding bit in this register is set is able to cause the channel interrupt flag HCIF in USBFS_GINTF register This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserve...

Page 815: ...eserved r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PP PLST 1 0 Reserved PRST PSP PREM Reserved PEDC PE PCD PCST rw r rw rs rw rc_w1 rc_w1 rc_w1 r Bits Fields Descriptions 31 19 Reserved Must be kept at reset value 18 17 PS 1 0 Port speed Report the enumerated speed of the device attached to this port 01 Full speed 10 Low speed Others Reserved 16 13 Reserved Must be kept at reset value 12 PP ...

Page 816: ...tected 0 Port is not in suspend state 1 Port is in suspend state 6 PREM Port resume Application sets this bit to start a resume signal on USB port Application should clear this bit when it wants to stop the resume signal 0 No resume driven 1 Resume driven 5 4 Reserved Must be kept at reset value 3 PEDC Port enable disable change Set by the core when the status of the Port enable bit 2 in this regi...

Page 817: ...tion and cleared by USBFS 0 Channel disabled 1 Channel enabled Software should following the operation guide to disable or enable a channel 30 CDIS Channel disable Software can set this bit to disable the channel from processing transactions Software should follow the operation guide to disable or enable a channel 29 ODDFRM Odd frame For periodic transfers interrupt or isochronous transfer this bi...

Page 818: ...acket length The target endpoint s maximum packet length Host channel x interrupt flag register USBFS_HCHxINTF x 0 7 where x channel number Address offset 0x0508 channel_number 0x20 Reset value 0x0000 0000 This register contains the status and events of a channel when software gets a channel interrupt it should read this register for the respective channel to know the source of the interrupt The f...

Page 819: ... conditions occurs during receiving a packet A received packet has a wrong CRC field A stuff error detected on USB bus Timeout when waiting for a response packet 6 Reserved Must be kept at reset value 5 ACK ACK An ACK response is received or transmitted 4 NAK NAK A NAK response is received 3 STALL STALL A STALL response is received 2 Reserved Must be kept at reset value 1 CH Channel halted This ch...

Page 820: ...erved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DTERIE REQOVRIE BBERIE USBERIE Reserved ACKIE NAKIE STALLIE Reserved CHIE TFIE rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 11 Reserved Must be kept at reset value 10 DTERIE Data toggle error interrupt enable 0 Disable data toggle error interrupt 1 Enable data toggle error interrupt 9 REQOVRIE Request queue overrun interrupt enable 0 D...

Page 821: ...interrupt enable 0 Disable transfer finished interrupt 1 Enable transfer finished interrupt Host channel x transfer length register USBFS_HCHxLEN x 0 7 where x channel number Address offset 0x0510 channel_number 0x20 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved DPID 1 0 PCNT 9 0 TLEN 18 16 rw rw rw 15 14 13 12 11 1...

Page 822: ...gth The total data byte number of a transfer For OUT transfers this field is the total data bytes of all the data packets desired to be transmitted in an OUT transfer Software should program this field before the channel is enabled When software successfully writes a packet into the channel s data TxFIFO this field is decreased by the byte size of the packet For IN transfer each time software read...

Page 823: ...ing a Set Address command from USB host 3 Reserved Must be kept at reset value 2 NZLSOH Non zero length status OUT handshake When a USB device receives a non zero length data packet during status OUT stage this field controls that either USBFS should receive this packet or reject this packet with a STALL handshake 0 Treat this packet as a normal packet and response according to the status of NAKS ...

Page 824: ...while Software should clear the GONAK flag before writing this bit again 8 CGINAK Clear global IN NAK Software sets this bit to clear GINS bit in this register 7 SGINAK Set global IN NAK Software sets this bit to set GINS bit in this register When GINS bit is zero setting this bit will also cause GINAK flag in USBFS_GINTF register triggered after a while Software should clear the GINAK flag before...

Page 825: ...o remote wakeup signal generated 1 Generate remote wakeup signal Device status register USBFS_DSTAT Address offset 0x0808 Reset value 0x0000 0000 This register contains status and information of the USBFS in device mode This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FNRSOF 13 8 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FNRSOF 7 0 Reserved ES ...

Page 826: ...terrupt in USBFS_DAEPINT register The bits in this register are set and cleared by software This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IEPNEEN Reserved EPTXFUDEN CITOEN Reserved EPDISEN TFEN rw rw rw rw rw Bits Fields Descriptions 31 7 Reserved Must be kept at reset value 6 IEPNEEN IN endpo...

Page 827: ... If a bit in this register is set by software the corresponding bit in USBFS_DOEPxINTF register is able to trigger an endpoint interrupt in USBFS_DAEPINT register The bits in this register are set and cleared by software This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BTBSTPEN Reserved EPRXFOVRE...

Page 828: ...transfer finished interrupt Device all endpoints interrupt register USBFS_DAEPINT Address offset 0x0818 Reset value 0x0000 0000 When an endpoint interrupt is triggered USBFS sets corresponding bit in this register and software should read this register to know which endpoint is asserting an interrupt This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Re...

Page 829: ...egister This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved OEPIE 3 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IEPIE 3 0 rw Bits Fields Descriptions 31 20 Reserved Must be kept at reset value 19 16 OEPIE 3 0 Out endpoint interrupt enable 0 Disable OUT endpoint n interrupt 1 Enable OUT endpoint n interrupt Each bit represents an OUT endp...

Page 830: ...at reset value 15 0 DVBUSDT 15 0 Device VBUS discharge time There is a discharge process after VBUS pulsing in SRP protocol This field defines the discharge time of VBUS The true discharge time is 1024 DVBUSDT 15 0 TUSBCLOCK where TUSBCLOCK is the period time of USB clock Device VBUS pulsing time register USBFS_DVBUSPT Address offset 0x082C Reset value 0x0000 05B8 This register has to be accessed ...

Page 831: ...register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IEPTXFEIE 3 0 rw Bits Fields Descriptions 31 4 Reserved Must be kept at reset value 3 0 IEPTXFEIE 3 0 IN endpoint Tx FIFO empty interrupt enable bits This field controls whether the TXFE bits in USBFS_DIEPxINTF registers are able to generate an endpoint...

Page 832: ...ble an endpoint 29 28 Reserved Must be kept at reset value 27 SNAK Set NAK Software sets this bit to set NAKS bit in this register 26 CNAK Clear NAK Software sets this bit to clear NAKS bit in this register 25 22 TXFNUM 3 0 Tx FIFO number Defines the Tx FIFO number of IN endpoint 0 21 STALL STALL handshake Software can set this bit to make USBFS sends STALL handshake when receiving IN token USBFS ...

Page 833: ...lue 1 0 MPL 1 0 Maximum packet length This field defines the maximum packet length for a control data packet As described in USB 2 0 protocol there are 4 kinds of length for control transfers 00 64 bytes 01 32 bytes 10 16 bytes 11 8 bytes Device IN endpoint x control register USBFS_DIEPxCTL x 1 3 where x endpoint_number Address offset 0x0900 endpoint_number 0x20 Reset value 0x0000 0000 This regist...

Page 834: ...For interrupt bulk IN endpoints Software sets this bit to clear DPID bit in this register 27 SNAK Set NAK Software sets this bit to set NAKS bit in this register 26 CNAK Clear NAK Software sets this bit to clear NAKS bit in this register 25 22 TXFNUM 3 0 Tx FIFO number Defines the Tx FIFO number of this IN endpoint 21 STALL STALL handshake Software can set this bit to make USBFS sends STALL handsh...

Page 835: ...acket 0 Only sends data in even frames 1 Only sends data in odd frames Endpoint data PID For interrupt bulk IN endpoints There is a data PID toggle scheme in interrupt or bulk transfer Set SD0PID to set this bit before a transfer starts and USBFS maintains this bit during transfers according to the data toggle scheme described in USB protocol 0 Data packet s PID is DATA0 1 Data packet s PID is DAT...

Page 836: ...t value 21 STALL STALL handshake Set this bit to make USBFS send STALL handshake during an OUT transaction USBFS will clear this bit after a SETUP token is received on OUT endpoint 0 This bit has a higher priority than NAKS bit in this register i e if both STALL and NAKS bits are set the STALL bit takes effect 20 SNOOP Snoop mode This bit controls the snoop mode of an OUT endpoint In snoop mode US...

Page 837: ...s 11 8 bytes Device OUT endpoint x control register USBFS_DOEPxCTL x 1 3 where x endpoint_number Address offset 0x0B00 endpoint_number 0x20 Reset value 0x0000 0000 The application uses this register to control the operations of each logical OUT endpoint other than OUT endpoint 0 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EPEN EPD SODDFRM SD1 PID...

Page 838: ...s register 27 SNAK Set NAK Software sets this bit to set NAKS bit in this register 26 CNAK Clear NAK Software sets this bit to clear NAKS bit in this register 25 22 Reserved Must be kept at reset value 21 STALL STALL handshake Software can set this bit to make USBFS sends STALL handshake during an OUT transaction This bit has a higher priority than NAKS bit in this register and GINAK in USBFS_DCTL...

Page 839: ...ata PID toggle scheme in interrupt or bulk transfer Software should set SD0PID to set this bit before a transfer starts and USBFS maintains this bit during transfers following the data toggle scheme described in USB protocol 0 Data packet s PID is DATA0 1 Data packet s PID is DATA1 15 EPACT Endpoint active This bit controls whether this endpoint is active If an endpoint is not active it ignores al...

Page 840: ...it or by setting CNAK bit in USBFS_DIEPxCTL register 5 Reserved Must be kept at reset value 4 EPTXFUD Endpoint Tx FIFO underrun This flag is triggered if the Tx FIFO has no packet data when an IN token is incoming 3 CITO Control IN Timeout interrupt This flag is triggered if the device waiting for a handshake is timeout in a control IN transaction 2 Reserved Must be kept at reset value 1 EPDIS End...

Page 841: ... control OUT endpoint This flag is triggered when a control out endpoint has received more than 3 back to back setup packets 5 Reserved Must be kept at reset value 4 EPRXFOVR Endpoint Rx FIFO overrun This flag is triggered if the OUT endpoint s Rx FIFO has no enough space for a packet data when an OUT token is incoming USBFS will drop the incoming OUT data packet and sends a NAK handshake in this ...

Page 842: ... enabled After the transfer starts this field is decreased automatically by USBFS after each successful data packet transmission 18 7 Reserved Must be kept at reset value 6 0 TLEN 6 0 Transfer length The total data byte number of a transfer This field is the total data bytes of all the data packets desired to be transmitted in an IN transfer Program this field before the endpoint is enabled When s...

Page 843: ... 20 Reserved Must be kept at reset value 19 PCNT Packet count The number of data packets desired to receive in a transfer Program this field before the endpoint is enabled After the transfer starts this field is decreased automatically by USBFS after each successful data packet reception on bus 18 7 Reserved Must be kept at reset value 6 0 TLEN 6 0 Transfer length The total data byte number of a t...

Page 844: ...ts 28 19 PCNT 9 0 Packet count The number of data packets desired to be transmitted in a transfer Program this field before the endpoint is enabled After the transfer starts this field is decreased automatically by USBFS after each successful data packet transmission 18 0 TLEN 18 0 Transfer length The total data byte number of a transfer This field is the total data bytes of all the data packets d...

Page 845: ...ld before setup transfers Each time a back to back setup packet is received USBFS decrease this field by one When this field reaches zero the BTBSTP flag in USBFS_DOEPxINTF register will be triggered 00 0 packet 01 1 packet 10 2 packets 11 3 packets 28 19 PCNT 9 0 Packet count The number of data packets desired to receive in a transfer Program this field before the endpoint is enabled After the tr...

Page 846: ...27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IEPTFS 15 0 r Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 IEPTFS 15 0 IN endpoint s Tx FIFO space remaining IN endpoint s Tx FIFO space remaining in 32 bit words 0 FIFO is full 1 1 word available n n words available 24 7 4 Power and clock control register USBFS_PWRCLKCTL Address offset 0...

Page 847: ... SHCLK SUCLK rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 SHCLK Stop HCLK Stop the HCLK to save power 0 HCLK is not stopped 1 HCLK is stopped 0 SUCLK Stop the USB clock Stop the USB clock to save power 0 USB clock is not stopped 1 USB clock is stopped ...

Page 848: ... as set this bit to 1 Writing 0 has no effect on the bit value read clear by read rc_r Software can read this bit Reading this bit automatically clears it to 0 Writing 0 has no effect on the bit value 25 2 List of terms Table 25 2 List of terms Glossary Descriptions Word Data of 32 bit length Half word Data of 16 bit length Byte Data of 8 bit length IAP in application programming Writing 0 has no ...

Page 849: ...GD32F10x User Manual 849 25 3 Available peripherals For availability of peripherals and their number across all MCU series types refer to the corresponding device data datasheet ...

Page 850: ...onfiguration register 0 AFIO_PCF0 3 Modify CAN RFO1 register access attributes in chapter Receive message FIFO1 register CAN_RFIFO1 4 Modify I2C register information in chapter Inter integrated circuit interface I2C 5 Add description of DAC output buffer refer to DAC output buffer 6 Modify the DBG_CTL register refer to Control register DBG_CTL 7 Modify the sleep mode wakeup description refer to Sl...

Page 851: ...ry remapped to address 0x00000000 in chapter Boot configuration 4 Add the maximum system clock description in chapter System and memory architecture and Reset and clock unit RCU 5 Modify the ADDSEND and MASTER bit description in Inter integrated circuit interface I2C registers 6 Move the descriptions about the Middle density High density Extra density and connectivity line to chapter System and me...

Page 852: ...2 Consistency update of Watchdog timer WDGT chapter 13 Modify register naming refers to MAC PHY data register ENET_MAC_PHY_DATA change CSR signal in ENET_MAC_CFG register to CRS signal 14 Delete descriptions about MSB or LSB data reception method for USART refers to Universal synchronous asynchronous receiver transmitter USART 15 Modify decription for Analog to digital converter ADC refers to Fore...

Page 853: ...y business industrial personal and or household applications only The Products are not designed intended or authorized for use as components in systems designed or intended for the operation of weapons weapons systems nuclear installations atomic energy control instruments combustion control instruments airplane or spaceship instruments transportation instruments traffic signal instruments life su...

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