GigaDevice Semiconductor GD32F10 Series, User Manual

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GD32F10x User Manual
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be transferred. After starting operating, the DMA controller will read five word addresses
which are 0x2000 0AB0, 0x2000 0AB4, 0x2000 0AB8, 0x2000 0ABC and 0x2000 0AC0. But
when sending data to the FIFO, the first two bytes (0x2000 0AB0 and 0x2000 0AB1) and the
last 3 bytes (0x2000 0AC1, 0x2000 0AC2 and 0x2000 0AC3) will be dropped.
Buffer Writing: Assuming the receive buffer address is 0x2000 0CD2, and 16 bytes need to
be stored. After starting operating, the DMA controller will write five times 32-bit data from
address 0x2000 0CD0 to 0x2000 0CE0. But the first 2 bytes (0x2000 0CD0 and 0x2000 0CD1)
and the last 2 bytes (0x2000 0CE2 and 0x2000 0CE3) will be substituted by the virtual bytes.
Note: DMA controller will not write any data out of the defined buffer range.
The effective length of the buffer
For the frame transmitting process, the effective length of the buffer is the same as the value
configured by application in TDES1. As mentioned before, a transmitting frame can use one
or more descriptors to indicate the frame information which means a frame data can be
located in many buffers. When the DMA controller reads a descriptor which the FSG bit in
TDES0 is set, it knows the current buffer is pointing to a new frame and the first byte of the
frame is included. When the DMA controller reads a descriptor with FSG bit and LSG bit in
TDES0 are both reset, it knows the current buffer is pointing to a part of current frame. When
the DMA controller reads a descriptor with LSG bit in TDES0 is set, it know the current buffers
is pointing to the last part of the current frame. Normally one frame is stored only in one buffer
(because buffer size is large enough for a normal frame), so FSG bit and LSG bit are set in
the same descriptor.
For the frame receiving process, the receive buffer size must be word align. But for word-align
buffer address or not word-align buffer address, the operation is different from transmitting.
When the receive buffer address is word align, it’s no difference with transmitting process,
the effective length of the buffer is the same as the value configured by application in RDES1.
When the receive buffer address is not word align, the effective length of the buffer is less
than the value configured by application in RDES1. The effective length of the buffer should
be the size value minus the low two bits value of buffer address. For example, assuming the
total buffer size is 2048 bytes and buffer address is 0x2000 0001, the low two bits are 0b01,
the effective length of the buffer is 2047 bytes whose address range is from 0x20000001 (for
the first received frame byte) to 0x2000 07FF.
When a start of frame (SOF) is received, the FSG bit is set by DMA controller and when the
end of the frame (EOF) is received, the LSG bit is set. If the receive buffer size is programmed
to be large enough to store the whole frame, the FSG and the LSG bit are set in the same
descriptor. The actual frame length FRML can be read from RDES0. So application can
calculate the left unused buffer space. The RxDMA always uses a new descriptor to receive
the start of next frame.