GD32F10x User Manual
239
12.4.
Register definition
DAC base address: 0x4000 7400
12.4.1.
Control register (DAC_CTL)
Address offset: 0x00
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
DDMAEN
1
DWBW1[3:0]
DWM1[1:0]
DTSEL1[2:0]
DTEN1
DBOFF1
DEN1
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DDMAEN
0
DWBW0[3:0]
DWM0[1:0]
DTSEL0[2:0]
DTEN0
DBOFF0
DEN0
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:29
Reserved
Must be kept at reset value
28
DDMAEN1
DAC1 DMA enable
0: DAC1 DMA mode disabled
1: DAC1 DMA mode enabled
27:24
DWBW1[3:0]
DAC1 noise wave bit width
These bits specify bit width of the noise wave signal of DAC1. These bits indicate
that unmask LFSR bit [n-1, 0] in LFSR noise mode or the amplitude of the triangle
is ((2<<(n-1))-1) in triangle noise mode, where n is the bit width of wave.
0000: The bit width of the wave signal is 1
0001: The bit width of the wave signal is 2
0010: The bit width of the wave signal is 3
0011: The bit width of the wave signal is 4
0100: The bit width of the wave signal is 5
0101: The bit width of the wave signal is 6
0110: The bit width of the wave signal is 7
0111: The bit width of the wave signal is 8
1000: The bit width of the wave signal is 9
1001: The bit width of the wave signal is 10
1010: The bit width of the wave signal is 11
≥
1011: The bit width of the wave signal is 12
23:22
DWM1[1:0]
DAC1 noise wave mode
Summary of Contents for GD32F10 Series
Page 63: ...GD32F10x User Manual 63 programmed during the chip production ...
Page 117: ...GD32F10x User Manual 117 010 1 0 011 0 9 ...
Page 416: ...GD32F10x User Manual 416 shadow register updates every update event ...
Page 427: ...GD32F10x User Manual 427 value ...
Page 518: ...GD32F10x User Manual 518 These bits are not used in SPI mode ...