GigaDevice Semiconductor GD32F10 Series, User Manual

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GD32F10x User Manual
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ETSL[31:16]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETSL[15:0]
rw
Bits Fields Descriptions
31:0 ETSL[31:0] Expected time low bits
These bits store the expected target nanosecond time (signed).
22.4.42.
DMA bus control register (ENET_DMA_BCTL)
Address offset: 0x1000
Reset value: 0x0000 2101
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved AA FPBL UIP RXDP[5:0] FB
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTPR[1:0] PGBL[5:0] Reserved DPSL[4:0] DAB SWR
rw rw rw rw rs
Bits Fields Descriptions
31:26 Reserved Must be kept at reset value.
25 AA Address-aligned bit
0: Disable address-aligned
1: Enabled address-aligned. If the FB=1, all AHB interface address is aligned to
the start address LS bits (bit 1 to 0). If the FB=0, the AHB interface first access
address (accessing the data buffer’s start address) is not aligned, but subsequent
burst access addresses are aligned to the address
24 FPBL Four times PGBL mode bit
0: The PGBL value programmed (bits [22:17] and bits [13:8]) for the DMA data
number of beats to be transferred
1: Multiple the PGBL value programmed (bits [22:17] and bits [13:8]) four times for
the DMA data number of beats to be transferred
23 UIP Use independent PGBL bit
0: The PGBL value in bits [13:8] is applicable for both TxDMA and RxDMA
engines
1: The RxDMA uses the RXDP[5:0] bits as burst length while the PGBL[5:0] is
used by TxDMA