GigaDevice Semiconductor GD32F10 Series, User Manual, Page: 736 / 853

GD32F10x User Manual
736
22.4.37.
PTP time stamp update high register (ENET_PTP_TSUH)
Address offset: 0x0710
Reset value: 0x0000 0000
This register configures the high 32-bit of the time to be written to, added to, or subtracted
from the system time value. The timestamp update registers (high and low) initialize or update
the system time maintained by the MAC core. Application must write both of these registers
before setting the TMSSTI or TMSSTU bits in the timestamp control register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TMSUS[31:16]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMSUS[15:0]
rw
Bits Fields Descriptions
31:0 TMSUS[31:0] Time stamp update second bits
These bits are used for initializing or adding/subtracting to second of the system
time
22.4.38.
PTP time stamp update low register (ENET_PTP_TSUL)
Address offset: 0x0714
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TMSUPNS TMSUSS[30:16]
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMSUSS[15:0]
rw
Bits Fields Descriptions
31 TMSUPNS Timestamp update positive or negative sign bit
When TMSSTI is set, this bit must be 0.
0: Timestamp update value is added to system time
1: Timestamp update value is subtracted from system time
30:0 TMSUSS[30:0] Timestamp update subsecond bits
These bits are used for initializing or adding/subtracting to subsecond of the
system time