GigaDevice Semiconductor GD32F10 Series, User Manual

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GD32F10x User Manual
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table is an implicitly one. Explicit chaining of descriptors is accomplished by configuring the
second address chained in both receive and transmit descriptors (RDES1[14] and
TDES0[20]), at this time RDES2 and TDES2 are stored the data buffer address, RDES3 and
TDES3 should be stored the next descriptor address, this connection method of descriptor
table is called chain structure. Implicitly chaining of descriptors is accomplished by clearing
the RDES1[14] and TDES0 [20], at this time RDES2, TDES2 and RDES3, TDES3 should be
all stored the data buffer address, this connection method of descriptor table is called ring
structure. When current de
scriptor’s buffer address is used, descriptor pointer will point to the
next descriptor. If chain structure is selected, the pointer points to the value of buffer 2. If ring
structure is selected, the pointer points to an address calculated as below:
Next descriptor address = Current descriptor a 16 + DPSL*4
If current descriptor is the last one in descriptor table, application needs to set the bit 21 in
TDES0 or bit 15 in RDES1 to inform DMA the current descriptor is the last one of the table in
ring structure. At this time, the next descriptor pointer points back to the first descriptor
address of the descriptor table. In chain structure, can also set TDES3 or RDES3 value to
point back to the first descriptor address of the descriptor table. The DMA skips to the next
frame buffer when the end of frame is detected.
Figure 22-8. Descriptor ring and chain structure
Descriptor 0
Descriptor 1
Descriptor 2
Descriptor n
Buffer 1
Buffer 2
Buffer 1
Buffer 2
Buffer 1
Buffer 2
Buffer 1
Buffer 2
Descriptor 0
Descriptor 1
Descriptor 2
Buffer 1
Buffer 1
Buffer 1
Next descriptor
Chain structure
Ring structure
If descriptor end
If descriptor end
...
.
Descriptor n
...
.
...
.
Alignment rule for data buffer address
The DMA controller supports all alignment types: byte alignment, half-word alignment and
word alignment. This means application can configure the buffer address to any address. But
during the operation of the DMA controller, access address is always word align and is
different between write and read access. Follow example describes the detail:
Buffer Reading: Assuming the transmit buffer address is 0x2000 0AB2, and 15 bytes need to