GigaDevice Semiconductor GD32F10 Series, User Manual

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GD32F10x User Manual
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of 32-bit words.
Figure 24-7. Device mode FIFO space in SRAM
.
.
.
Rx FIFO
Tx FIFO0
Tx FIFO1
IEPTX0RSAR[15:0]
IEPTX0FD
IEPTX1FD
IEPTX1RSAR[15:0]
RXFD
Start: 0x00
End: 0x13F
Tx FIFO3
IEPTX3FD
IEPTX3RSAR[15:0]
USBFS provides a special register area for the internal data FIFO reading and writing. Figure
24-8. Device mode FIFO access register map describes the register memory area where
the data FIFO can access. The addresses in the figure are addressed in bytes. Each endpoint
has its own FIFO access register space. Rx FIFO is also able to be accessed by using
USBFS_GRSTATR/USBFS_GRSTATP register.
Figure 24-8. Device mode FIFO access register map
IEP0 FIFO Write
IEP1 FIFO Write
1000h-1FFFh
IEP3 FIFO Write
...
2000h-2FFFh
4000h-4FFFh
Can be read by any
OUT endpoint FIFO