GigaDevice Semiconductor GD32F10 Series, User Manual

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GD32F10x User Manual
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Figure 1-1. The structure of the Cortex
®
-M3 processor
Nested
Vectored
Interrupt
Controller
(NVIC)
Cortex-M3 core
Flash Patch
Breakpoint
(FPB)
Cortex-M3 processor
Data
Watchpoint
And Trace
(DWT)
AHB
Access port
(AHB-AP)
Bus Matrix
Instrumentation
Trace Macrocell
(ITM)
Embedded
Trace
Macrocell
(ETM)
Trace Port
Interface Unit
(TPIU)
Serial-Wire
Or JTAG
Debug Port
(SWDP or
SWJ-DP)
CoreSight
ROM table
Wake-up
Interrupt
Controller
(WIC)
Interrupts and
Power control
Trace
Port
Interface
System
AHB-Lite
System
interface
DCode
AHB-Lite
Data
interface
ICode
AHB-Lite
Data
interface
Serial-Wire or
JTAG Debug
Interface
PPB APB
Debug system
interface
Note: The functions of ETM and MPU do not exist in the GD32F101xx and GD32F103xx
microcontrollers
with the flash memory density less than 256 Kbytes.
1.2. System architecture
A 32-bit multilayer bus is implemented in the GD32F10x devices, which enables parallel
access paths between multiple masters and slaves in the system. The multilayer bus consists
of an AHB interconnect matrix, one AHB bus and two APB buses. The interconnection
relationship of the AHB interconnect matrix is shown below. In the following table,
“1” indicates
the corresponding master is able to access the corresponding slave through the AHB
interconnect matrix, while the blank means the corresponding master cannot access the
corresponding slave through the AHB interconnect matrix. This architecture is shown in Table
1-1. The interconnection relationship of the AHB interconnect matrix
Table 1-1. The interconnection relationship of the AHB interconnect matrix
IBUS DBUS SBUS DMA0 DMA1 ENET
FMC-I 1
FMC-D 1 1 1
SRAM 1 1 1 1 1 1