GigaDevice Semiconductor GD32F10 Series, User Manual

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GD32F10x User Manual
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bit_word_addr = 0x2200 0000 + (0x200 * 32)+ (7 * 4)= 0x2200 401C (1-2)
Writing to address 0x2200 401C will cause bit 7 of address 0x2000 0200 change while a read
to address 0x2200 401C will return 0x01 or 0x00 according to the value of bit 7 at the SRAM
address 0x2000 0200.
1.3.2.
On-chip SRAM memory
The GD32F10x series of devices contain up to 96 KB of on-chip SRAM which starts at the
address 0x2000 0000. It supports byte, half-word (16 bits), and word (32 bits) accesses.
1.3.3.
On-chip flash memory overview
The devices provide high density on-chip flash memory, which is organized as follows:
■
Up to 3072KB of main flash memory.
■
Up to 18KB of information blocks for the boot loader.
■
Option bytes to configure the device.
GD32F101xx and GD32F103xx microcontrollers where the flash memory density ranges
between 16 and 128 Kbytes are called Medium-density devices (GD32F10x_MD).
GD32F101xx and GD32F103xx microcontrollers where the flash memory density ranges
between 256 and 512 Kbytes are called High-density devices (GD32F10x_HD).
GD32F101xx and GD32F103xx microcontrollers where the flash memory density is over 512
Kbytes are called Extra-density devices (GD32F10x_XD).
GD32F105xx and GD32F107xx microcontrollers are called connectivity line devices
(GD32F10x_CL).
Refer to Flash memory controller (FMC) Chapter for more details.
1.4. Boot configuration
The GD32F10x devices provide three kinds of boot sources which can be selected by the
BOOT0 and BOOT1 pins. The details are shown in Table 1-3. Boot modes . The value on
the two pins is latched on the 4th rising edge of CK_SYS after a reset. It is up to the user to
set the BOOT0 and BOOT1 pins after a power-on reset or a system reset to select the
required boot source. Once the two pins have been sampled, they are free and can be used
for other purposes.
Table 1-3. Boot modes
Selected boot source
Boot mode selection pins
Boot1 Boot0
Main Flash Memory x 0