GigaDevice Semiconductor GD32F10 Series, User Manual

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GD32F10x User Manual
658

Support Ethernet frame time stamping for both transmit and receive operation, which
describes in IEEE 1588-2008, and 64 bit time stamps are given in each f
rame’s status.

Two independent FIFO of 2K Byte for transmitting and receiving.

Support special condition frame discards handling, e.g. late collision, excessive collisions,
excessive deferral or underrun.

Calculate and insert IPv4 header checksum and TCP, UDP, or ICMP checksum in frame
transmit under Store-and-Forward mode.
DMA Feature

Two types of descriptor addressing: Ring and Chain.

Each descriptor can transfer up to 8 KB of data.

Programmable normal and abnormal interrupt for many status conditions.

Round-robin or fixed-priority arbitration between reception and transmission controller.
PTP Feature

Support IEEE 1588 time synchronization function.

Support two correction methods: Coarse or Fine.

Pulse per second output.

Preset target time reaching trigger and interrupt.
22.2.1.
Block diagram
The Ethernet module is composed of a MAC module, MII/RMII module and a DMA module
by descriptor control.
Figure 22-1. ENET module block diagram
AHB
Arbiter
MII
Interf
ace
TxDM
A
RxDM
A
TxMTL
(2k tbuf)
RxMTL
(2k tbuf)
TxMA
C
RxMA
C
M
u
x
MSC Ethernet Reg
Time Stamp Gen
(PTP IEEE 1588)
Station
Management
RMII
Interf
ace
A
H
B
M
a
st
e
r I
F
A
H
B
S
la
v
e
IF
E
th
e
rn
e
t P
h
y
The MAC module is connected to the external PHY by MII or RMII through one selection bit
(refer to AFIO_PCF0 register). The SMI (Station Management Interface) is used to configure
and manage external PHY.
Transmitting data module includes:

TxDMA controller, used to read descriptors and data from memory and writes status to
memory.