GigaDevice Semiconductor GD32F10 Series, User Manual

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GD32F10x User Manual
100
2 SRAMSPEN SRAM interface clock enable when sleep mode
This bit is set and reset by software to enable/disable SRAM interface clock during
Sleep mode.
0: Disabled SRAM interface clock during Sleep mode.
1: Enabled SRAM interface clock during Sleep mode
1 DMA1EN DMA1 clock enable
This bit is set and reset by software.
0: Disabled DMA1 clock
1: Enabled DMA1 clock
0 DMA0EN DMA0 clock enable
This bit is set and reset by software.
0: Disabled DMA0 clock
1: Enabled DMA0 clock
5.3.7.
APB2 enable register (RCU_APB2EN)
Address offset: 0x18
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
TIMER10
EN
TIMER9E
N
TIMER8E
N
Reserved
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC2EN
USART0
EN
TIMER7E
N
SPI0EN
TIMER0E
N
ADC1EN ADC0EN PGEN PFEN PEEN PDEN PCEN PBEN PAEN Reserved AFEN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits Fields Descriptions
31:22 Reserved Must be kept at reset value
21 TIMER10EN TIMER10 clock enable
This bit is set and reset by software.
0: Disabled TIMER10 clock
1: Enabled TIMER10 clock
20 TIMER9EN TIMER9 clock enable
This bit is set and reset by software.
0: Disabled TIMER9 clock
1: Enabled TIMER9 clock
19 TIMER8EN TIMER8 clock enable
This bit is set and reset by software.