GigaDevice Semiconductor GD32F10 Series, User Manual

Page: 583 / 853

GD32F10x User Manual
583
Figure 20-1. The EXMC block diagram
AHB Bus Interface
EXMC Configuration
Register
NAND-Flash/PC Card
Controller
NOR-Flash/PSRAM
Controller
E
X
M
C
_
CD
E
X
M
C
_
N
IO
S
16
E
X
M
C
_
N
IO
R
D
E
X
M
C
_
IN
T
R
E
X
M
C
_
N
C
E
[2
:1
]
E
X
M
C
_
N
W
E
E
X
M
C
_
N
C
E
3
_
1
E
X
M
C
_
IN
T
[2
:1
]
E
X
M
C
_
N
W
A
IT
E
X
M
C
_
N
C
E
3
_
0
E
X
M
C
_
N
O
E
E
X
M
C
_
N
IO
W
R
E
X
M
C
_
C
L
K
E
X
M
C
_
NL
(o
r
N
A
D
V
)
E
X
M
C
_
A
[25
:0
]
E
X
M
C
_
NE
[3
:0
]
E
X
M
C
_
N
B
L
[1
:0
]
E
X
M
C
_
D
[15
:0
]
PC Card
Pins
NAND
Pins
HCLK
from clock
controller
EXMC
interrupt
to NVIC
NOR/PSRA
M Pins
PSRAM
Pins
Share
d Pins
NOR/PSR
AM/NAND
Shared Pin
E
X
M
C
_
N
R
E
G
20.3.2.
Basic regulation of EXMC access
EXMC is the conversion interface between AHB bus and external device protocol. 32-bit of
AHB read/write accesses can be split into several consecutive 8-bit or 16-bit read/write
operations respectively. In the process of data transfer, AHB access data width and memory
data width may not be the same. In order to ensure consistency of data transmission, EXMC’s
read/write accesses follows the following basic regulation.

When the width of AHB bus equals to the memory bus width, no conversion is applied.

When the width of AHB bus is greater than memory bus width, the AHB accesses will
automatically split into several continuous memory accesses.

When the width of AHB bus is smaller than memory bus width, if the external memory
devices have the byte selection function, such as SRAM, ROM. PSRAM, the application
can access the corresponding byte through their byte lane EXMC_NBL[1:0]. Otherwise,
write operation is prohibited, but read operation is allowed unconditionally.