GigaDevice Semiconductor GD32F10 Series, User Manual, Page: 593 / 853

GD32F10x User Manual
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Figure 20-9. Mode A write access
Address
(EXMC_A[25:0])
Byte Lane Select
(EXMC_NBL[1:0])
Chip Enable
(EXMC_NEx)
Output Enable
(EXMC_NOE)
Write Enable
(EXMC_NWE)
Data
(EXMC_D[15:0])
Address Setup Time
(WASET+1 HCLK)
Data Setup Time
(WDSET HCLK)
EXMC Output
1 HCLK
The different between mode A and mode 1 write timing is that read/write timing is specified
by the same set of timing configuration, while mode A write timing configuration is
independent of its read configuration.
Table 20-7. Mode A related registers configuration
Bit Position Bit Name Reference Setting Value
EXMC_SNCTLx
31-20 Reserved 0x000
19 SYNCWR 0x0
18-16 Reserved 0x0
15 ASYNCWAIT Depends on memory
14 EXMODEN 0x1
13 NRWTEN 0x0
12 WREN Depends on user
11 NRWTCFG No effect
10 WRAPEN 0x0
9 NRWTPOL Meaningful only when the bit 15 is set to 1
8 SBRSTEN 0x0
7 Reserved 0x1
6 NREN No effect
5-4 NRW Depends on memory
3-2 NRTP Depends on memory, except 2(Nor Flash)
1 NRMUX 0x0
0 NRBKEN 0x1
EXMC_SNTCFGx(Read)
31-30 Reserved 0x0
29-28 ASYNCMOD 0x0
27-24 DLAT No effect
23-20 CKDIV No effect