GigaDevice Semiconductor GD32F10 Series, User Manual

Page: 137 / 853

GD32F10x User Manual
137
5 TIMER6EN TIMER6 clock enable
This bit is set and reset by software.
0: Disabled TIMER6 clock
1: Enabled TIMER6 clock
4 TIMER5EN TIMER5 clock enable
This bit is set and reset by software.
0: Disabled TIMER5 clock
1: Enabled TIMER5 clock
3 TIMER4EN TIMER4 clock enable
This bit is set and reset by software.
0: Disabled TIMER4 clock
1: Enabled TIMER4 clock
2 TIMER3EN TIMER3 clock enable
This bit is set and reset by software.
0: Disabled TIMER3 clock
1: Enabled TIMER3 clock
1 TIMER2EN TIMER2 clock enable
This bit is set and reset by software.
0: Disabled TIMER2 clock
1: Enabled TIMER2 clock
0 TIMER1EN TIMER1 clock enable
This bit is set and reset by software.
0: Disabled TIMER1 clock
1: Enabled TIMER1 clock
5.6.9.
Backup domain control register (RCU_BDCTL)
Address offset: 0x20
Reset value: 0x0000 0018, reset by backup domain reset.
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
Note: The LXTALEN, LXTALBPS, RTCSRC and RTCEN bits of the backup domain control
register (RCU_BDCTL) are only reset after a backup domain Reset. These bits can be
modified only when the BKPWEN bit in the power control register (PMU_CTL) is set.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved BKPRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN Reserved RTCSRC[1:0] Reserved
LXTALBP
S
LXTALST
B
LXTALEN
rw rw rw r rw