GigaDevice Semiconductor GD32F10 Series, User Manual

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GD32F10x User Manual
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1: When update event occurs, the DMA request of channel x is sent.
2:0 Reserved Must be kept at reset value.
Slave mode configuration register (TIMERx_SMCFG)
Address offset: 0x08
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP SMC1 ETPSC[1:0] ETFC[3:0] MSM TRGS[2:0] Reserved SMC[2:0]
rw rw rw rw rw rw rw
Bits Fields Descriptions
31:16 Reserved Must be kept at reset value
15 ETP External trigger polarity
This bit specifies the polarity of ETI signal
0: ETI is active at rising edge or high level .
1: ETI is active at falling edge or low level .
14 SMC1 Part of SMC for enable External clock mode1.
In external clock mode 1, the counter is clocked by any active edge on the ETIFP
signal.
0: External clock mode 1 disabled
1: External clock mode 1 enabled.
When the slave mode is configured as restart mode, pause mode or event mode,
the timer can still work in the external clock 1 mode by setting this bit. But the TRGS
bits must not be 3’b111 in this case.
The clock source of the timer will be ETIFP if external clock mode 0 and external
clock mode 1 are configured at the same time.
Note:
External clock mode 0 enable is in this register’s SMC[2:0] bit-filed.
13:12 ETPSC[1:0] The prescaler of external trigger
The frequency of external trigger signal ETIFP must not be at higher than 1/4 of
TIMER_CK frequency. When the external trigger signal is a fast clock, the prescaler
can be enabled to reduce ETIFP frequency.
00: Prescaler disable.
01: The prescaler is 2.
10: The prescaler is 4.