GD32F10x User Manual
260
RTC_INTEN register, the RTC will generate an alarm interrupt when the system time equals
to the alarm time (stored in the RTC_ALRMH/L register),
Figure 14-1. Block diagram of RTC
RTC_DIV
RTC_PSC
RTC_CNT
RTC_ALRM
COMPARE
APB interface
SCIF
SCIE
OVIF
OVIE
ALRMIF
ALRMIE
NVIC
interrupt
controler
APB1 BUS
RTCCLK
Reload
SC_CLK
RTC_Second
RTC_Overf low
RTC_Alarm
Rising edge
EXIT STANDBY MODE
EXTI LI NE 17
HXTAL
/
128
LXTAL
IRC40K
RTCSRC[1:0]
BACKUP DOMAIN
PCLK1
RTC
Interrupt
14.3.1.
RTC reset
The APB interface and the RTC_INTEN register are reset by system reset. The RTC core
(prescaler, divider, counter and alarm) is reset only by a backup domain reset.
Steps to enable access to the backup registers and the RTC after reset are as follows:
1.
Set the PMUEN and BKPIEN bits in the RCU_APB1EN register to enable the power and
backup interface clocks.
2.
Enable access to the backup registers and RTC by setting the BKPWEN bit in the
(PMU_CTL).
14.3.2.
RTC reading
The APB interface and RTC core are located in two different power supply domains.
In the RTC core, only counter and divider registers are readable registers. And the values in
the two registers and the RTC flags are internally updated at each rising edge of the RTC
clock, which is resynchronized by the APB1 clock.
When the APB interface is immediately enabled from a disable state, the read operation is
not recommended because the first internal update of the registers has not finished. That
means, when a system reset, power reset, waking up from Standby mode or Deep-sleep
mode occurs, the APB interface was in disabled state, but the RTC core has been kept
running. In these cases, the correct read operation should first clear the RSYNF bit in the
RTC _CTL register and wait for it to be set by hardware. While WFI and WFE have no effects
on the RTC APB interface.
14.3.3.
RTC configuration
The
RTC_PSC, RTC_CNT and RTC_ALRM registers in the RTC core are writable. These
Summary of Contents for GD32F10 Series
Page 63: ...GD32F10x User Manual 63 programmed during the chip production ...
Page 117: ...GD32F10x User Manual 117 010 1 0 011 0 9 ...
Page 416: ...GD32F10x User Manual 416 shadow register updates every update event ...
Page 427: ...GD32F10x User Manual 427 value ...
Page 518: ...GD32F10x User Manual 518 These bits are not used in SPI mode ...