Toshiba TMPR4925, Руководство пользователя

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Chapter 4 Address Mapping
4-2
4.2 Register Map
4.2.1 Addressing
TX4925 internal registers are to be accessed through 64 K bytes address space that is based on
physical address 0xFF1F_0000 or pointed address by RAMP register (refer to 5.2.11). Figure 4.2.1
shows how to generate internal register address. Physical address 1 and physical address 2 shown
Figure 4.2.1 access the same register.
In TX49/H2 Core, the physical address form 0xFF00_0000 to 0xFF3F_FFFF are unchached mapped
to the virtual address form 0xFF00_0000 to 0xFF3F_FFFF.
This space includes the region form 0xFF1F_0000 allocated TX4925 internal registers at
initialization.
Figure 4.2.1 Generating Physical Address for a Internal Register
4.2.2 Ways to Access to Internal Registers
2 ways to access to the internal registers of TX4925 are supported. First is 32-bit register access.
Second is PCI configuration register access in PCI satellite mode.
32-bit register supports 32-bit size access only. Another size access without 32-bit size is undefined.
When the build-in PCI controller works in the satellite mode (refer to “10.3.1 Terminology
Explanation”), PCI configuration registers are to be accessed through PCI bus in configuration cycles. It
is possible to access to the arbitrary size of PCI configuration register as always Little Endian space
regardless the system setup.
Base Address
(0xFF1F_0000)
Offset Address
+
Physical Address 1
=
Base Address Register
(RAMP)
Offset Address Physical Address 2
(Initial Value = 0xFF1F_0000)
+ =