Toshiba TMPR4925, Руководство пользователя

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Chapter 7 External Bus Controller
7-14
7.3.7.2 ACK * /READY Input/Output Switching Timing
When in the ACK*/Ready Static mode, the ACK*/Ready signal is always an input signal. When
in the ACK*/Ready Dynamic mode, the ACK*/Ready signal is an input signal when in the
External ACK mode or the Ready mode, but is an output signal in all other modes.
During External ACK mode or Ready mode access, the ACK* signal becomes High-Z at the
cycle where the CE* signal is asserted. At the end of the access cycle, the ACK* signal is output
(driven) again one clock cycle after the CE* signal is deasserted (see Figure 7.3.3).
7.3.7.3 ACK * Output Timing (Normal Mode, Page Mode)
When in the Normal mode and Page mode of the ACK*/Ready Dynamic mode, the ACK*
signal becomes an output signal and is asserted for one clock cycle to send notification to the
external device of the data Read and data Write timing.
During the Read cycle, the data is latched at the rise of the next clock cycle after when the
ACK* signal is asserted. (See Figure 7.3.7 ACK* Output Timing (Single Read Cycle) ).
During the Write cycle, SWE*/BWE* is deasserted at the next clock cycle after when the ACK*
signal is deasserted, and the data is held for one more clock cycle after that. (See Figure 7.3.8
ACK* Output Timing (Single Write Cycle) ).
Figure 7.3.7 ACK * Output Timing (Single Read Cycle)
Figure 7.3.8 ACK * Output Timing (Single Write Cycle)
1 clock
SYSCLK
CE
*
ADDR [19 : 0]
OE
*
DATA [31:0]
ACK * /READY
(Output)
Data is latched
EBCCRn.PWT:WT=2
EBCCRn.SHWT=0
SYSCLK
CE
*
ADDR [19 : 0]
SWE */ BWE *
DATA [31
:
0]
ACK * /READY
(Output)
2 clocks
EBCCRn.PWT:WT=2
EBCCRn.SHWT=0
1 clock