Toshiba TMPR4925, Руководство пользователя

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Chapter 8 DMA Controller
8-22
8.4.1 DMA Master Control Register (DMMCR) 0xB0A8
This register controls the entire DMA Controller.
31 28 27 24 23 20 19 16
EIS[3:0] DIS[3:0] Reserved FIFOVC
R R R : Type
0000 0000 000000 : Initial value
15 14 13 11 10 8 7 6 3 2 1 0
FIFVC FIFWP FIFRP
RSFIF
FIFUM[3:0]
Reserved RRPT MSTEN
R R R/W R/W R/W R/W : Type
000 000 0 0000 0 0 : Initial value
Bits Mnemonic Field Name Description
31:28 EIS[3:0] Error Interrupt
Status Error Interrupt Status [3:0] (Initial value: 0x0, R)
These four bits indicate the error interrupt status of each channel. EIS[n] corresponds
to channel
n .
1: There is an error interrupt in the corresponding channel.
0: There is no error interrupt in the corresponding channel.
27:24 DIS[3:0] Normal
Completion
Interrupt Status Done Interrupt Status [3:0] (Initial value: 0x0, R)
These four bits indicate the transfer completion (transfer complete or chain ended)
interrupt status of each channel. DIS[n] corresponds to channel
n .
1: There is a transfer completion interrupt in the corresponding channel.
0: There is no transfer completion interrupt in the corresponding channel.
23:20
⎯
Reserved
⎯
19:14 FIFVC FIFO Valid Entry
Count FIFO Valid Entry Count (Initial value: 000000, R)
These read only bits indicate the byte count of data that were written to FIFO but not
read out from the FIFO.
13:11 FIFWP FIFO Write
Pointer FIFO Write Pointer (Initial value: 000, R)
These read only bits indicate the next write position in FIFO. This is a diagnostic
function.
10:8 FIFRP
FIFO Read
Pointer
FIFO Read Pointer (Initial value: 000, R)
These read only bits indicate the next read position in FIFO. This is a diagnostic
function.
7 RSFIF Reset FIFO Reset FIFO (Initial value: 0, R/W)
This bit is used for resetting FIFO. When this bit is set to “1”, the FIFO read pointer,
FIFO write pointer and FIFO valid entry count are initialized to “0”.
If an error occurs during DMA transfer, use this bit when data remains in the FIFO
(when the FIFO Valid entry Count Field is not “0”) to initialize the FIFO.
Figure 8.4.1 DMA Master Control Register (1/2)