Toshiba TMPR4925, Руководство пользователя

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Chapter 10 PCI Controller
10-75
10.4.46 P2G Memory Space 0 Control Register (P2GM0CTR) 0xD184
31 29 28 20 19 16
Reserved AM[28:20] Reserved
R/W : Type
0x03F : Initial value
15 11 10 8 7 5 4 3 2 1 0
Reserved TPRBL Reserved TMCC
Reserved
MEMOPD
P2GM0EN
BSWAP
R/W R/W R/W R/W R/W R/W : Type
010 0 1 1 0 0/1 : Initial value
Bits Mnemonic Field Name Description
31:29
⎯
Reserved
⎯
28:20 AM[28:20] Address Mask PCI-Bus to G-Bus Address Mask (Initial value: 0x03F, R/W)
Sets the bits to be subject to address comparison. See 10.3.4 for more information.
When setting a memory space size of 256 MB (0x1000_0000) for example, the value
becomes 0x0FF.
19:11
⎯
Reserved
⎯
10:8 TPRBL Target Prefetch
Read Burst
Length Target Prefetch Read Burst Length (Initial value: 0x3, R/W)
These bits set the G-Bus Burst Size (in DWORDS, (32-bit words)) to be read into the
data FIFO during a target memory Read operation.
0x000: Access and transfer 1DWORD (NO BURST)
0x001: Access and transfer 4 DWORDs of data to the target read FIFO.
0x010: Access and transfer 8 DWORDs of data to the target read FIFO.
0x011: Access and transfer 16 DWORDs of data to the target read FIFO.
0x1xx: Access and transfer 32 DWORDs of data to the target read FIFO.
7:5
⎯
Reserved
⎯
4 TMCC Target Memory
space 0 Cache
Clear Target Memory space 0 Cache Clear (Initial value: 0, R/W)
A write of 1 will flush the Target Memory Cache 0. This bit is cleared automatically.
1: Cache Clear
0: Don’t care
3
⎯
Reserved Note: This bit is always set to “0”. (Initial value: 1, R/W)
2 MEM0PE Memory 0
Window Prefetch
Enable Memory 0 Window Prefetch Enable (Initial value: 1, R/W)
If this bit is set, Prefetching of G-Bus data will occur on Target Memory Reads. If this
bit is cleared, 1 Burst of length TPRBL will be done on the G-Bus.
Even if the setting of this bit is changed, prefetchable bits in the Base Address
Register of the PCI Configuration Space will not reflect this change. We recommend
using the default setting when the PCI Controller is in the Satellite mode.
1 P2GM0EN Memory Space 0
Enable Target Memory Space 0 Enable (Initial value: 0, R/W) Controls whether Memory
Space 0 for target access is valid or invalid.
When this bit is set to invalid, Writes to the Memory Space 0 Base Address Register
of the PCI Configuration Register become invalid. Also, “0” is returned to Reads as a
response.
1: Validates Memory Space 0 for target access.
0: Invalidates Memory Space 0 for target access.
0 BSWAP Byte Swap Byte Swap Enable
(Initial value: Little Endian Mode: 0; Big Endian Mode: 1, R/W) Sets the byte swapping
of Memory Space 0 for target access..
0: Do not perform byte swapping.
1: Perform byte swapping.
Please use the default state in most situations. If this bit is changed to “0” when in the
Big Endian Mode, the byte order of transfer to Memory Space 0 through DWORD (32-
bit) access will not change.
Figure 10.4.46 P2G Memory Space 0 Control Register