Toshiba TMPR4925, Руководство пользователя

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Chapter 11 Serial I/O Port
11-20
11.4.5 FIFO Control Register 0 (SIFCR0) 0xF310 (Ch. 0)
FIFO Control Register 1 (SIFCR1) 0xF410 (Ch. 1)
These registers set control of the Transmit/Receive FIFO buffer.
31 16
0
: Type
: Initial value
15 14 9 8 7 6 5 4 3 2 1 0
SWRST
0 RDIL 0 TDIL
TFRST RFRST FRSTE
R/W R/W R/W R/W R/W R/W : Type
0 00 00 0 0 0 : Initial value
Bits Mnemonic Field Name Description
31:16
⎯
Reserved
⎯
15 SWRST Software Reset Software Reset (Initial value: 0, R/W)
This field performs SIO resets except for the FIFOs. Setting this bit to “1” initiates the
reset. Set registers are also initialized. This bit returns to “0” when initialization is
complete.
0: Normal operation
1: SIO software reset
14:9
⎯
Reserved
⎯
8:7 RDIL Receive FIFO
Request Trigger
Level Receive FIFO DMA/Interrupt Trigger Level (Initial value: 00, R/W)
This register sets the level for reception data transfer from the Receive FIFO.
00: 1 Byte
01: 4 Bytes
10: 8 Bytes
11: 12 Bytes
6:5
⎯
Reserved
⎯
4:3 TDIL Transmit FIFO
Request Trigger
Level Transmit FIFO DMA/Interrupt Trigger Level (Initial value: 00, R/W)
This register sets the level for transmission data transfer to the Transmit FIFO.
00: 1 Byte
01: 4 Bytes
10: 8 Bytes
11: Setting disabled
2 TFRST Transmit FIFO
Reset Transmit FIFO Reset (Initial value: 0, R/W)
The Transmit FIFO buffer is reset when this bit is set. This bit is valid when the FIFO
Reset Enable bit (FRSTE) is set. Cancel reset by using the software to clear this bit.
0: During operation
1: Reset Transmit FIFO
1 RFRST Receive FIFO
Reset Receive FIFO Reset (Initial value: 0, R/W)
The Receive FIFO buffer is reset when this bit is set. This bit is valid when the FIFO
Reset Enable bit (FRSTE) is set. Cancel reset by using the software to clear this bit.
0: During operation
1: Reset Receive FIFO
0 FRSTE FIFO Reset
Enable FIFO Reset Enable (Initial value: 0, R/W)
This field is the Reset Enable for the Transmit/Receive FIFO buffer. The FIFO is reset
by combining the Transmit FIFO Reset bit (TFRST) and Receive FIFO Reset bit
(RRST).
0: During operation
1: Reset Enable
Figure 11.4.5 FIFO Control Register