Toshiba TMPR4925, Руководство пользователя

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Chapter 10 PCI Controller
10-6
10.3.3 Supported PCI Bus Commands
Table 10.3.1 shows the PCI Bus commands that the PCI Controller supports.
Table 10.3.1 Supported PCI Bus Commands
C/BE Value PCI Command As Initiator As Target
0000 Interrupt Acknowledge †
⎯
0001 Special Cycle †
⎯
0010 I/O Read
√ √
0011 I/O Write
√ √
0100 (Reserved)
⎯ ⎯
0101 (Reserved)
⎯ ⎯
0110 Memory Read
√ √
0111 Memory Write
√ √
1000 (Reserved)
⎯ ⎯
1001 (Reserved)
⎯ ⎯
1010 Configuration Read
√
‡
1011 Configuration Write
√
‡
1100 Memory Read Multiple
√ √
1101 Dual Address Cycle
⎯ ⎯
1110 Memory Read Line
√ √
1111 Memory Write and Invalidate
√ √
Note: In the case of I/O read, I/O write, single access memory read and memory write, the
required byte enables are asserted. In the case of burst access memory read, 4-byte
enables are asserted.
√
: Supported when in both the Host mode and the Satellite mode
† : Supported only when in the Host mode
‡ : Supported only when in the Satellite mode
— : Not supported
•
I/O Read, I/O Write, Memory Read, Memory Write
This command executes Read/Write access to the address mapped on the G-Bus and PCI Bus.
•
Memory Read Multiple, Memory Read Line
The Memory Read Multiple command is issued if all of the following conditions are met when
the Initiator function is operating and Burst Read access is issued from the G-Bus to the PCI Bus.
(1) A value other than “0” is set to the Cache Line Size Field (PCICFG1.CLS) of the PCI
Configuration 1 Register.
(2) The Read data word count is larger than the value set in the Cache Line Size Field.
Also, the Read Memory Line command is issued when all of the following conditions are met.
(1) A value other than “0” is set to the Cache Line Size Field (PCICFG1.CLS) of the PCI
Configuration 1 Register.
(2) The Read data word count is larger than the value set in the Cache Line Size Field.