Toshiba TMPR4925, Руководство пользователя

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Chapter 10 PCI Controller
10-7
The Memory Read command is issued if these conditions are not met, namely, if “0” is set to the
Cache Line Size field (PCICFG1.CLS) of the PCI Configuration 1 Register. In the case of the
target, a normal G-Bus cycle is issued to the address mapped from the PCI Bus to the G-Bus.
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Memory Write and Invalidate
When the TX4925 operates as the initiator, the PCI Controller issues the Memory Write and
Invalidate command if all of the following conditions are met when write access from the G-Bus to
the PCI Bus occurs.
(1) The Memory Write and Invalidate Enable bit (PCISTATUS.MWIEN) of the PCI Status
Command Register is set.
(2) A value other than “0” was set to the Cache Line Size field (PCICFG1.CLS) of the PCI
Configuration 1 Register.
(3) The word count of the Write data is larger than the value set in the Cache Line Size field.
The Memory Write command is issued in these conditions are not met.
When the TX4925 operates as the target, the Memory Write and Invalidate command is
converted into G-Bus Write access. Note that the TX4925 does not support the cache memory
Snoop function.
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Configuration Read, Configuration Write
The corresponding configuration cycles are issued on the PCI Bus. This is done by either
reading or writing from/to the G2P Configuration Data Register (G2PCFGDATA) after writing the
configuration space address to the G2P Configuration Address Register. The TX4925 supports both
“Type 0” and “Type 1” configuration transactions.
On systems that have PCI card slots, the PCI Host device checks each PCI card slot during
system initialization to see if PCI device exist, then sets the Configuration Space Register of the
devices that do exist. If a PCI Configuration Read operation is performed for devices that do not
exist, then by default a Bus Error exception will be generated since there is no PCI Bus response.
Clearing the Bus Error Response During Initiator Read bit (G2PCFG.IRBER) of the PCI Controller
Configuration Register makes it possible to execute a Read transaction without causing a Bus
Error. All bits of the data read at this time will be set to “1”.
Configuration cycles will be accepted as the target only when in the Satellite mode. After reset,
Retry response to PCI Configuration access will continue until the software sets the Target
Configuration Access Ready Bit (PCICFG.TCAR) of the PCI Controller Configuration Register.
Please use the software to set this bit after the software initialization process ends and the software
is ready to accept PCI configuration.
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Interrupt Acknowledge
This command issues interrupt acknowledge cycles as an initiator only when in the Host mode.
Interrupt acknowledge cycles are executed on the PCI Bus when the G2P Interrupt Acknowledge
Data Register (G2PINTACK) is read. The value returned by this Read becomes the interrupt
acknowledge cycle data.
The TX4925 does not support interrupt acknowledge cycles as the target.