Toshiba TMPR4925, Руководство пользователя

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Chapter 10 PCI Controller
10-18
(3) Chain Enable bit checking
Reads the value of the Chain Enable bit (CHNEN) in the PDMAC Configuration Register
(PDMCFG). If the read value is “0”, then the Chain Address field value of the DMA
Command Descriptor indicated by the address stored in the PDMAC Chain Address Register
(PDMCA) is written to the PDMAC Chain Address Register (PDMCA).
10.3.9.4 Data Transfer Mode
The Transfer Mode field in the PDMAC Configuration register (PDMCFG.XFRMODE) selects
a data transfer mode for a DMA transaction over the G-Bus. Transfer data size and when a transfer
is started differ mode by mode.
Table 10.3.7 shows the available data transfer modes. Mode 00 performs a single-beat transfer;
Mode 01 performs a burst transfer. In either mode, the PDMAC reads data from the source
address, and after the read cycles are complete, writes the data to the destination address. Source
read and destination write cycles do not overlap.
Table 10.3.7 Data Transfer Modes
G-Bus to the PCI bus
PDMCFG.X
FRMODE
Free FIFO Space
Required for
G-Bus Read
Accesses
(DWORDs)
Number of
DWORDs Read
from the G-Bus
Number of
DWORDs required
in FIFO for PCI
Bus Write
Accesses
Number of
DWORDs Written
to the PCI Bus
Overlaps of PCI
Bus and G-Bus
Cycles
00 1 1 1 1 None
01 16 16 (Burst)
*
1
16 16 (Burst) None
PCI Bus to the G-Bus
PDMCFG.X
FRMODE
Free FIFO Space
Required for
G-Bus Write
Accesses
(DWORDs)
Number of
DWORDs Written
to the G-Bus
Number of
DWORDs
Required in FIFO
for PCI Bus Read
Accesses
Number of
DWORDs Read
from the PCI Bus
Overlaps of PCI
Bus and G-Bus
Cycles
00 1 1 1 1 None
01 16 16 (Burst)
*
1
16 16 (Burst) None
* 1: The last DMA transfer consists of less than 16 DWORDs if the data to be transferred is not a
multiple of 16 DWORDs.
Note: The amount of data transferred varies, depending on the number of DWORDs present in the
FIFO.