Toshiba TMPR4925, Руководство пользователя

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Chapter 10 PCI Controller
10-9
When expressed as a formula, conversion of a G-Bus address (GBusAddr[31:0]) into a PCI Bus
Address (PCIAddr[31:0]) is as follows below. GBASE[31:8], PBASE[31:8], and AM[28:8] each
represent the setting register of the corresponding access window indicated below in Table 10.3.2. The
“&” symbol indicates a logical AND for each bit, “||” indicates a logical OR for each bit, “!” indicates
logical NOT, and “|” indicates bit linking.
If ((GBusAddr[31:29] | (GBusAddr[28:8] & ! AM[28:8] == GBASE[31:29] | (GBASE[28:8] & ! AM[28:8]) then
PCIAddr[31:0] = PBASE[31:29] | ((PBASE[28:8] & ! AM[28:8]) || (GBusAddr[28:8] & AM[28:8]))
| GBusAddr[7:0];
Table 10.3.2 Initiator Access Space Address Mapping Register
G-Bus Base Address
GBASE[31:8]
PCI Bus Base Address
PBASE[31:8]
Address Mask
AM[28:8]
Memory Space 0 G2PM0GBASE.BA[31:8] G2PM0PBASE.BA[31:8] G2PM0MASK.AM[28:8]
Memory Space 1 G2PM1GBASE.BA[31:8] G2PM1PBASE.BA[31:8] G2PM1MASK.AM[28:8]
Memory Space 2 G2PM2GBASE.BA[31:8] G2PM2PBASE.BA[31:8] G2PM2MASK.AM[28:8]
I/O Space G2PIOGBASE.BA[31:8] G2PIOPBASE.BA[31:8] G2PIOMASK.AM[28:8]
Figure 10.3.4 illustrates this address conversion.
Figure 10.3.4 Address Conversion For Initiator (G-Bus
→
PCI Bus Address Conversion)
It is possible to set each space to valid/invalid or to perform Word Swap (see “10.3.7 Endian
Switching Function”). Table 10.3.3 shows the settings registers for these properties.
Also, operation is not guaranteed if resources in the PCI space were made cacheable and were then
accessed when the Critical Word First function of the TX49/H2 core was enabled.
GBusAddr
0
31
0x00
0
31
7 8
Compare
GBASE
0x00
0
31
7 8
AM
000 000 - - - - - - - - - - - 0 0 1 1 1 - - - - - - - - - - - - - - -
0x00
0
31
7 8
PBASE
0 31
PCIAddr
29 28