Toshiba TMPR4925, Руководство пользователя

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Chapter 10 PCI Controller
10-23
10.3.13 Set Configuration Space
In Table 10.5.1, the values for the registers inside the PCI Configuration Space Register that have a
gray background can be rewritten using one of the following method.
10.3.13.1 Set the Configuration Space Using Software Reset
By using the following procedure, it is possible to use the software to set the configuration
space.
(1) Set the value to be loaded in the Configuration Data 0 Register (PCICDATA0), the
Configuration Data 1 Register (PCICDATA1), the Configuration Data 2 Register
(PCICDATA2), and the Configuration Data 3 Register (PCICDATA3).
(2) Clear the Load Configuration Data Register bit (LCFG) of the PCI Controller Configuration
Register (PCICCFG).
After these processes are complete, please set the Target Configuration Access Ready bit
(PCICCFG.TCAR) of the PCI Controller Configuration Register to be able to accept access to the
PCI Configuration space.
10.3.14 PCI Clock Signal
The configuration setting via ADDR[18] during boot-up determines whether or not the clock from the
on-chip PLL is driven out from the PCI Clock outputs, PCICLK[2:1] and PCICLKIO. When ADDR[18]
is High, PCICLK[2:1] and PCICLKIO are configured as outputs. When ADDR[18] is Low,
PCICLK[2:1] are forced to the High-Z state and PCICLKIO is configured as an input.
When PCICLK[2:1] and PCICLKIO are configured as outputs, the PCFG.PCICLKIOEN bit must not
be cleared. When configured as an output, the PCIC internally feeds back PCICLKIO as a PCI bus
clock to adjust the phase of the clock. However, if the PCFG.PCICLKEN[2:1] and PCFG.PCICLKIOEN
bits are cleared, PCICLK[2:1] and PCICLKIO are held Low respectively. (see Figure 6.1.1).