Toshiba TMPR4925, Руководство пользователя

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Chapter 10 PCI Controller
10-25
Table 10.4.1 PCI Controller Control Register (2/2)
Section Address Bit Width Mnemonic Register Name
10.4.39 0xD158 32 G2PM1PBASE G2P Memory Space 1 PCI Base Address Register
10.4.40 0xD160 32 G2PM2PBASE G2P Memory Space 2 PCI Base Address Register
10.4.41 0xD168 32 G2PIOPBASE G2P I/O Space PCI Base Address Register
10.4.42 0xD170 32 PCICCFG PCI Controller Configuration Register
10.4.43 0xD174 32 PCICSTATUS PCI Controller Status Register
10.4.44 0xD178 32 PCICMASK PCI Controller Interrupt Mask Register
10.4.45 0xD180 32 P2GM0GBASE P2G Memory Space 0 G-Bus Base Address Register
10.4.46 0xD184 32 P2GM0CTR P2G Memory Space 0 Control Register
10.4.47 0xD188 32 P2GM1GBASE P2G Memory Space 1 G-Bus Base Address Register
10.4.48 0xD18C 32 P2GM1CTR P2G Memory Space 1 Control Register
10.4.49 0xD190 32 P2GM2GBASE P2G Memory Space 2 G-Bus Base Address Register
10.4.50 0xD194 32 P2GM2CTR P2G Memory Space 2 Control Register
10.4.51 0xD198 32 P2GIOGBASE P2G I/O Space G-Bus Base Address Register
10.4.52 0xD19C 32 P2GIOCTR P2G IO Space Control Register
10.4.53 0xD1A0 32 G2PCFGADRS G2P Configuration Address Register
10.4.54 0xD1A4 32 G2PCFGDATA G2P Configuration Data Register
⎯
0xD1B0
⎯ ⎯
(Reserved)
⎯
0xD1B8
⎯ ⎯
(Reserved)
⎯
0xD1C0
⎯ ⎯
(Reserved)
10.4.55 0xD1C8 32 G2PINTACK G2P Interrupt Acknowledge Data Register
10.4.56 0xD1CC 32 G2PSPC G2P Special Cycle Data Register
10.4.57 0xD1E0 32 PCICDATA0 Configuration Data 0 Register
10.4.58 0xD1E4 32 PCICDATA1 Configuration Data 1 Register
10.4.59 0xD1E8 32 PCICDATA2 Configuration Data 2 Register
10.4.60 0xD1EC 32 PCICDATA3 Configuration Data 3 Register
10.4.61 0xD200 32 PDMCA PDMAC Chain Address Register
10.4.62 0xD204 32 PDMGA PDMAC G-Bus Address Register
10.4.63 0xD208 32 PDMPA PDMAC PCI Bus Address Register
10.4.64 0xD20C 32 PDMCTR PDMAC Count Register
10.4.65 0xD210 32 PDMCFG PDMAC Configuration Register
10.4.66 0xD214 32 PDMSTATUS PDMAC Status Register