Toshiba TMPR4925, Руководство пользователя

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Chapter 10 PCI Controller
10-1
10. PCI Controller
10.1 Features
The TX4925 PCI Controller functions as a bus bridge between the TX4925 External PCI and the internal
bus (G-Bus).
10.1.1 Overall
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Compliant to “PCI Local Bus Specification Revision 2.2”
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PCI Bus: 32-bit data bus; Internal Bus: 32-bit data bus
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Maximum PCI bus clock operating frequency: 33 MHz
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Supports both the Initiator and Target functions
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Supports power management functions that are compliant to PCI Bus Power Management
Interface Specifications Version 1.1 (Partially unsupported).
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On-chip PCI Bus Arbiter, can connect to a maximum of four external bus masters
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1-channel on-chip DMA Controller (PDMAC) dedicated to the PCI Controller
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Supports PCI clock input mode/output mode
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The Internal Bus clock and PCI Bus clock are asynchronous and can be set independently
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Includes function for booting the TX4925 from memory on the PCI Bus
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Can set configuration data by software at the initialize routine
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Mounted a retry function on the Internal Bus side also in order to avoid deadlock on the PCI Bus.
10.1.2 Initiator Function
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Single and Burst transfer from the Internal Bus to the PCI Bus
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Initiator function Supports memory, I/O, configuration, special cycle, and interrupt acknowledge
transactions.
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Address mapping between the Internal Bus and the PCI Bus can be modified
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Mounted 8-stage 32-bit data one FIFO each for Read and Write
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Indirect Read and Write function enables quick termination of single transactions by the G-Bus
without waiting for completion on the PCI Bus.
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Endian switching function
10.1.3 Target Function
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Single and Burst transfer from the PCI Bus to the Internal Bus
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Supports memory, I/O, and configuration cycles
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Supports high-speed back-to-back transactions on the PCI Bus
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Address mapping between the PCI Bus and the Internal bus can be modified
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Mounted 32-stage 32-bit data FIFO on each PCI Channel for Read
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Mounted 16-stage 32-bit data FIFO for Write
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Post Write function enables quick termination of a maximum of eight Write transactions by the PCI
Bus without waiting for completion on the G-Bus.
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Read Burst length (pre-fetch data size) on the Internal Bus when reading a pre-fetchable space can
be made programmable
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Endian switching function