Toshiba TMPR4925, Руководство пользователя

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Chapter 16 CHI Module
16-18
16.4.1 CHI Control Register (CTRL) 0xA800
31 30 29 28 27 26 25 24 20 19 16
Reserved LOOP TEST FDIR FWID CHAN TBOF
R/W R/W R/W R/W R/W R/W : Type
0 0 0 00 00000 0000 : Initial value
15 12 11 10 9 8 7 6 5 4 3 2 1 0
RBOF TMSB RMSB RFPL TFPL REDG TEDG FEDG TFED C2X REN TEN CEN
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W : Type
0000 0 0 0 0 0 0 0 0 0 0 0 0 : Initial value
Bits Mnemonic Field Name Description
31:30
⎯
Reserved
⎯
29 LOOP CHILOOP CHILOOP bit (Initial value: 0, R/W)
This bit is used for IC testing and should not be set. Setting this bit to a logic “1”
will cause the CHI serial transmitted data to be internally looped back to the CHI
serial receive data path. The data is inverted when this mode is selected. Clearing
this bit to a logic “0” selects the normal CHIDIN pin as the CHI serial receive data
source.
28 TEST CHIENTEST CHIENTEST bit (Initial value: 0, R/W)
This bit is used for IC testing and should not be set.
27 FDIR CHIFSDIR CHIFSDIR bit (Initial value: 0, R/W)
This bit controls the direction of the CHIFS pin.
0: CHIFS to be an input.(CHI sync slave mode) Note *
1: CHIFS to be an output.(CHI sync master mode)
Note that CHIRXFSPOL and CHIFSEDGE bits must be set to proper values even
when CHIFSDIR is set to a logic “1” (CHI sync master mode).
26:25 FWID[1:0] CHIFSWIDTH CHIFSWIDTH bits (Initial value: 00, R/W)
These bits are used to select pulse width for the CHIFS signal, relevant whenever
the CHI Module is configured as master mode. The pulse width is counted by data
bit width. (In clk2x mode, two CHICLKs correspond to one data bit.) The available
CHIFS pulse widths are as follows
00: 1 bit wide
01: 2 bits wides
10: 1 byte wide
11: half-frame wide
24:20 CHAN[4:0] CHINCHAN CHINCHAN bits (Initial value: 00000, R/W)
These bits are used to program the number of 8-bit channel timeslots per half-
frame, up to 32 total per half-frame. The value loaded for CHINCHAN is the
desired number of channels-1.
19:16 TBOF[3:0] CHTXBOFF CHITXBOFF bits (Initial value: 0000, R/W)
These bits select the transmit data programmable bit offset, which is related to the
number of clocks from the start of timeslot 0 (1st timeslot) transmit data to the
CHIFS edge used to trigger the start of each CHI frame. The value loaded for
CHITXBOFF must be chosen from Table 16.3.3 according to the configuration.
15:12 RBOF[3:0] CHIRXBOFF CHIRXBOFF bits (Initial value: 0000, R/W)
These bits select the receive data programmable bit offset, which is related to the
number of clocks from the start of timeslot 0 (1st timeslot) receive data to the
CHIFS edge used to trigger the start of each CHI frame. The value loaded for
CHIRXBOFF must be chosen from Table 16.3.2 according to the configuration.
11 TMSB TXMSBFIRST TXMSBFIRST bit (Initial value: 0, R/W)
This bit selects between MSB-first and LSB-first serial data formats for each byte
of the CHI transmit data.
0: LSB-first
1: MSB-first
Figure 16.4.1 Control Register (CTRLREG) (1/3)