NXP Semiconductors LPC84x, Руководство пользователя

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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 507 of 515
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NXP Semiconductors
UM11029
Chapter 32: Supplementary information
Chapter 8: LPC84x System configuration (SYSCON)
8.1 How to read this chapter . . . . . . . . . . . . . . . . . 79
8.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8.3 Basic configuration . . . . . . . . . . . . . . . . . . . . . 79
8.3.1 Set up the FRO. . . . . . . . . . . . . . . . . . . . . . . . 79
8.3.2 Set up the PLL . . . . . . . . . . . . . . . . . . . . . . . . 80
8.3.3 Configure the main clock and system clock . . 80
8.3.4 Set up the system oscillator using XTALIN and
XTALOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.5 General description . . . . . . . . . . . . . . . . . . . . . 82
8.5.1 Clock generation. . . . . . . . . . . . . . . . . . . . . . . 82
8.5.2 Power control of analog components . . . . . . . 85
8.5.3 Configuration of reduced power-modes . . . . . 86
8.5.4 Reset and interrupt control . . . . . . . . . . . . . . . 86
8.6 Register description . . . . . . . . . . . . . . . . . . . . 86
8.6.1 System memory remap register . . . . . . . . . . . 89
8.6.2 System PLL control register . . . . . . . . . . . . . . 89
8.6.3 System PLL status register. . . . . . . . . . . . . . . 90
8.6.4 System oscillator control register . . . . . . . . . . 90
8.6.5 Watchdog oscillator control register . . . . . . . . 91
8.6.6 FRO oscillator control register . . . . . . . . . . . . 92
8.6.7 FRO direct clock source update register . . . . 92
8.6.8 System reset status register . . . . . . . . . . . . . . 93
8.6.9 System PLL clock source select register . . . . 93
8.6.10 System PLL clock source update register . . . 94
8.6.11 Main clock PLL source select register . . . . . . 94
8.6.12 Main clock PLL source update enable register 94
8.6.13 Main clock source select register . . . . . . . . . . 95
8.6.14 Main clock source update enable register . . . 95
8.6.15 System clock divider register . . . . . . . . . . . . . 95
8.6.16 ADC clock source select register . . . . . . . . . . 96
8.6.17 ADC clock divider register . . . . . . . . . . . . . . . 96
8.6.18 SCT clock source select register . . . . . . . . . . 96
8.6.19 SCT clock divider register. . . . . . . . . . . . . . . . 96
8.6.20 External clock source select register . . . . . . . 97
8.6.21 System clock control 0 register . . . . . . . . . . . 97
8.6.22 System clock control 1 register . . . . . . . . . . 100
8.6.23 Peripheral reset control 0 register . . . . . . . . 100
8.6.24 Peripheral reset control 1 register . . . . . . . . 102
8.6.25 Peripheral clock source select registers . . . . 104
8.6.26 Fractional generator 0 divider value register 104
8.6.27 Fractional generator 0 multiplier value register . .
105
8.6.28 FRG0 clock source select register . . . . . . . . 106
8.6.29 Fractional generator 1 divider value register 106
8.6.30 Fractional generator 1 multiplier value register . .
107
8.6.31 FRG1 clock source select register . . . . . . . . 107
8.6.32 CLKOUT clock source select register . . . . . 108
8.6.33 CLKOUT clock divider register. . . . . . . . . . . 108
8.6.34 External trace buffer command register . . . 109
8.6.35 POR captured PIO0 status register 0 . . . . . 109
8.6.36 POR captured PIO1 status register 1 . . . . . 109
8.6.37 IOCON glitch filter clock divider registers 6 to 0 .
109
8.6.38 BOD control register . . . . . . . . . . . . . . . . . . . 110
8.6.39 System tick counter calibration register . . . . . 110
8.6.40 IRQ latency register . . . . . . . . . . . . . . . . . . . . 111
8.6.41 NMI source selection register . . . . . . . . . . . . 111
8.6.42 Pin interrupt select registers . . . . . . . . . . . . . 112
8.6.43 Start logic 0 pin wake-up enable register . . . 112
8.6.44 Start logic 1 interrupt wake-up enable register . .
113
8.6.45 Deep-sleep mode configuration register . . . . 115
8.6.46 Wake-up configuration register . . . . . . . . . . . 115
8.6.47 Power configuration register . . . . . . . . . . . . . 116
8.6.48 Device ID register . . . . . . . . . . . . . . . . . . . . . 118
8.7 Functional description . . . . . . . . . . . . . . . . . . 118
8.7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
8.7.2 Brown-out detection . . . . . . . . . . . . . . . . . . . . 118
8.7.3 System PLL functional description. . . . . . . . 120
8.7.3.1 Lock detector . . . . . . . . . . . . . . . . . . . . . . . . 120
8.7.3.2 Power-down control . . . . . . . . . . . . . . . . . . . 121
8.7.3.3 Divider ratio programming . . . . . . . . . . . . . . 121
8.7.3.3.1 Post divider . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.7.3.3.2 Feedback divider . . . . . . . . . . . . . . . . . . . . . 121
8.7.3.3.3 Changing the divider values. . . . . . . . . . . . . 121
8.7.3.4
Frequency selection. . . . . . . . . . . . . . . . . . . 121
8.7.3.4.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . 122
8.7.3.4.2 PLL Power-down mode . . . . . . . . . . . . . . . . 122
Chapter 9: LPC84x FRO API ROM routine
9.1 How to read this chapter . . . . . . . . . . . . . . . . 123
9.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.3 General description . . . . . . . . . . . . . . . . . . . . 123
9.4 API description . . . . . . . . . . . . . . . . . . . . . . . 125
9.4.1 set_fro_frequency . . . . . . . . . . . . . . . . . . . . 125
9.4.1.1 Param0: frequency. . . . . . . . . . . . . . . . . . . . 125