NXP Semiconductors LPC84x, Руководство пользователя

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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 247 of 515
NXP Semiconductors
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Chapter 15: LPC84x Reduced power modes and power management
15.5 General description
Power on the LPC84x is controlled by the PMU, by the SYSCON block, and the ARM
Cortex-M0+ core. The following reduced power modes are supported in order from
highest to lowest power consumption:
1. Sleep mode:
The sleep mode affects the ARM Cortex-M0+ core only. Peripherals and memories
are active.
2. Deep-sleep and power-down modes:
The deep-sleep and power-down modes affect the core and the entire system with
memories and peripherals. Before entering deep-sleep or power-down, you must
switch the main clock to the FRO to provide a clock signal that can be shut down
cleanly.
a. In deep-sleep mode, the peripherals receive no internal clocks. The flash is in
standby mode. The SRAM memory and all peripheral registers as well as the
processor maintain their internal states. The WWDT, WKT, and BOD can remain
active to wake up the system on an interrupt.
b. In power-down mode, the peripherals receive no internal clocks. The internal
SRAM memory and all peripheral registers as well as the processor maintain their
internal states. The flash memory is powered down. The WWDT, WKT, and BOD
can remain active to wake up the system on an interrupt.
3. Deep power-down mode:
For maximal power savings, the entire system is shut down except for the general
purpose registers in the PMU and the self-wake-up timer. Only the general purpose
registers in the PMU maintain their internal states. The part can wake up on a pulse
on either the WAKEUP pin or the RESET pin, or when the self-wake-up timer times
out. On wake-up, the part reboots.
Remark:
The part is in active mode when it is fully powered and operational after booting.
15.5.1 Wake-up process
If the part receives a wake-up signal in any of the reduced power modes, it wakes up to
the active mode.
See these links for related registers and wake-up instructions:
• To configure the system after wake-up: Table 171 “Wake-up configuration register
(PDAWAKECFG, address 0x4004 8234) bit description” .
•
To use external interrupts for wake-up: Table 168 “Start logic 0 pin wake-up enable
register 0 (STARTERP0, address 0x4004 8204) bit description” and Table 167 “Pin
interrupt select registers (PINTSEL[0:7], address 0x4004 8178 (PINTSEL0) to 0x4004
8194 (PINTSEL7)) bit description”
•
To enable external or internal signals to wake up the part from deep-sleep or
power-down modes:
Table 169 “Start logic 1 interrupt wake-up enable register
(STARTERP1, address 0x4004 8214) bit description”
•
To configure the USART to wake up the part: Section 17.3.2 “Configure the USART
for wake-up”