UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
467 of 515
NXP Semiconductors
UM11029
Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC)
26.7.4.2 Threshold-Compare Out-of-Range Interrupt
Every conversion performed on any channel is automatically compared against a
designated set of low and high threshold levels specified in the THRn_HIGH and
THRn_LOW registers. The results of this comparison on any individual channel(s) can be
enabled to cause a threshold-compare interrupt if that result was above or below the
range specified by the two thresholds or, alternatively, if the result represented a crossing
of the low threshold in either direction.
This flag must be cleared by a software write to clear the individual THCMP flags in the
FLAGS register.
26.7.4.3 Data Overrun Interrupt
This interrupt request will be asserted if any of the OVERRUN bits in the individual
channel data registers are set. In addition, the OVERRUN bits in the two sequence global
data (SEQn_GDAT) registers will cause this interrupt request IF the MODE bit for that
sequence is set to 0 (conversion-complete mode).
This flag will be cleared when the OVERRUN bit that caused it is cleared via reading the
register containing it.
Note that the OVERRUN bits in the individual data registers are cleared when data related
to that channel is read from either of the global data registers as well as when the
individual data registers themselves are read.
26.7.5 Optional operating modes
The following optional mode of A/D operation may be selected in the CTRL register:
Low-power mode. When this mode is selected, the analog portions of the ADC are
automatically shut down when no conversions are in progress. The ADC is automatically
restarted whenever any hardware or software trigger event occurs. This mode can save
an appreciable amount of power when the ADC is not in continuous use, but at the
expense of a delay between the trigger event and the onset of sampling and conversion.
26.7.6 DMA control
The sequence-A or sequence-B conversion/sequence-complete interrupts may also be
used to generate a DMA trigger. To trigger a DMA transfer, the same conditions must be
met as the conditions for generating an interrupt (see
and
Remark:
If the DMA is used, the ADC interrupt must be disabled in the NVIC.
For DMA transfers, only burst requests are supported. The burst size can be set to one in
the DMA channel control register (see
). If the number of ADC channels is not
equal to one of the other DMA-supported burst sizes (applicable DMA burst sizes are 1, 4,
8), set the burst size to one.
The DMA transfer size determines when a DMA interrupt is generated. The transfer size
can be set to the number of ADC channels being converted. Non-contiguous channels
can be transferred by the DMA using the scatter/gather linked lists.
