NXP Semiconductors LPC84x, Руководство пользователя

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User manual Rev. 1.0 — 16 June 2017 430 of 515
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Chapter 24: LPC84x Multi-Rate Timer (MRT)
24.6.1 Time interval register
This register contains the MRT load value and controls how the timer is reloaded. The
load value is IVALUE -1.
Table 426. Register overview: MRT (base address 0x4000 4000)
Name Access Address
offset Description Reset value Reference
INTVAL0 R/W 0x0 MRT0 Time interval value register. This value is
loaded into the TIMER0 register. 0 Table 427
TIMER0 R 0x4 MRT0 Timer register. This register reads the value
of the down counter. 0x7FFF FFFF Table 428
CTRL0 R/W 0x8 MRT0 Control register. This register controls the
MRT0 modes. 0 Table 429
STAT0 R/W 0xC MRT0 Status register. 0 Table 430
INTVAL1 R/W 0x10 MRT1 Time interval value register. This value is
loaded into the TIMER1 register. 0 Table 427
TIMER1 R/W 0x14 MRT1 Timer register. This register reads the value
of the down counter. 0x7FFF FFFF Table 428
CTRL1 R/W 0x18 MRT1 Control register. This register controls the
MRT1 modes. 0 Table 429
STAT1 R/W 0x1C MRT1 Status register. 0 Table 430
INTVAL2 R/W 0x20 MRT2 Time interval value register. This value is
loaded into the TIMER2 register. 0 Table 427
TIMER2 R/W 0x24 MRT2 Timer register. This register reads the value
of the down counter. 0x7FFF FFFF Table 428
CTRL2 R/W 0x28 MRT2 Control register. This register controls the
MRT2 modes. 0 Table 429
STAT2 R/W 0x2C MRT2 Status register. 0 Table 430
INTVAL3 R/W 0x30 MRT3 Time interval value register. This value is
loaded into the TIMER3 register. 0 Table 427
TIMER3 R/W 0x34 MRT3 Timer register. This register reads the value
of the down counter. 0x7FFF FFFF Table 428
CTRL3 R/W 0x38 MRT3 Control register. This register controls the
MRT modes. 0 Table 429
STAT3 R/W 0x3C MRT3 Status register. 0 Table 430
IDLE_CH R 0xF4 Idle channel register. This register returns the
number of the first idle channel. 0 Table 431
IRQ_FLAG R/W 0xF8 Global interrupt flag register 0 Table 432