UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
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1.1 Introduction
The LPC84x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at
CPU frequencies of up to 30 MHz. The LPC84x support up to 64 KB of flash memory and
16 KB of SRAM.
The peripheral complement of the LPC84x includes a CRC engine, four I
2
C-bus
interfaces, up to five USARTs, up to two SPI interfaces, one multi-rate timer, self-wake-up
timer, SCTimer/PWM, one general purpose 32-bit counter/timer, a DMA, one 12-bit ADC,
two 10-bit DACs, one analog comparator, function-configurable I/O ports through a switch
matrix, an input pattern match engine, and up to 54 general-purpose I/O pins.
Remark:
For additional documentation, see
1.2 Features
•
System:
–
ARM Cortex-M0+ processor (revision r0p1), running at frequencies of up to
30 MHz with single-cycle multiplier and fast single-cycle I/O port.
–
ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
–
System tick timer.
–
AHB multilayer matrix.
–
Serial Wire Debug (SWD) with four break points and two watch points. JTAG
boundary scan (BSDL) supported.
–
Micro Trace Buffer (MTB)
•
Memory:
–
Up to 64 KB on-chip flash programming memory with 64 Byte page write and
erase.
–
Fast Initialization Memory (FAIM) allowing the user to configure chip behavior on
power-up.
–
Code Read Protection (CRP).
–
Up to 16 KB SRAM consisting of two 8 KB contiguous SRAM banks. One 8 KB of
SRAM can be used for MTB.
–
Bit-band addressing supported to permit atomic operations to modify a single bit.
•
ROM API support:
–
Bootloader.
–
Supports Flash In-Application Programming (IAP).
–
Supports In-System Programming (ISP) through USART, SPI, and I
2
C.
–
FAIM API.
–
FRO API.
–
Flash In-Application Programming (IAP) and In-System Programming (ISP).
UM11029
Chapter 1: LPC84x Introductory information
Rev. 1.0 — 16 June 2017
User manual
