NXP Semiconductors LPC84x, Руководство пользователя

Страница: 256 / 515

UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 256 of 515
NXP Semiconductors
UM11029
Chapter 15: LPC84x Reduced power modes and power management
–
BOD interrupt using the deep-sleep interrupt wake-up register 1 ( Table 169 ). The
BOD interrupt must be enabled in the NVIC. The BOD interrupt must be selected in
the BODCTRL register.
–
Reset from the BOD circuit. In this case, the BOD circuit must be enabled in the
PDSLEEPCFG register, and the BOD reset must be enabled in the BODCTRL
register (
Table 163 ).
• WWDT signal, if the watchdog oscillator is enabled in the PDSLEEPCFG register:
–
WWDT interrupt using the interrupt wake-up register 1 ( Table 169 ). The WWDT
interrupt must be enabled in the NVIC. The WWDT interrupt must be set in the
WWDT MOD register, and the WWDT must be enabled in the SYSAHBCLKCTRL
register.
–
Reset from the watchdog timer. The WWDT reset must be set in the WWDT MOD
register. In this case, the watchdog oscillator must be running in deep-sleep mode
(see PDSLEEPCFG register), and the WDT must be enabled in the
SYSAHBCLKCTRL register.
•
Via any of the USART blocks if the USART is configured in synchronous mode. See
Section 17.3.2 “Configure the USART for wake-up” .
•
Via the I2C. See Section 19.3.3 .
• Via any of the SPI blocks. See Section 18.3.1 .
Remark:
If the BOD is enabled in active mode and the user needs to disable the BOD in
deep-sleep mode, disable the BOD reset (bit 4 in the BODCTRL register) before entering
power-down mode. After wake-up, enable the BOD reset (bit 4 in the BODCTRL register).
15.7.6 Power-down mode
In power-down mode, the system clock to the processor is disabled as in sleep mode. All
analog blocks are powered down, except for the BOD circuit and the watchdog oscillator,
which must be selected or deselected during power-down mode in the PDSLEEPCFG
register. The main clock and therefore all peripheral clocks are disabled except for the
clock to the watchdog timer if the watchdog oscillator is selected. The FRO itself and the
flash are powered down, decreasing power consumption compared to deep-sleep mode.
Power-down mode eliminates all power used by analog peripherals and all dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses. The processor state and registers, peripheral registers, and internal SRAM values
are maintained, and the logic levels of the pins remain static. Wake-up times are longer
compared to the deep-sleep mode.
15.7.6.1 Power configuration in power-down mode
Power consumption in power-down mode can be configured by the power configuration
setting in the PDSLEEPCFG (
Table 170 ) register in the same way as for deep-sleep mode
(see Section 15.7.5.1 ):
•
The watchdog oscillator can be left running in power-down mode if required for the
WWDT.
• The BOD circuit can be left running in power-down mode if required by the
application.