UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
465 of 515
NXP Semiconductors
UM11029
Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC)
hardware triggers. Each sequence can be triggered by a different hardware trigger. One of
these conversion sequences is referred to as the A sequence and the other as the B
sequence. It is not necessary to employ both sequences.
An optional single-step mode allows advancing through the channels of a sequence one
at a time on each successive occurrence of a trigger.
The user can select whether a trigger on the B sequence can interrupt an
already-in-progress A sequence. The B sequence, however, can never be interrupted by
an A trigger.
26.7.2 Hardware-triggered conversion
Software can select which of these hardware triggers will launch each conversion
sequence and it can specify the active edge for the selected trigger independently for
each conversion sequence.
For each conversion sequence, if a designated trigger event occurs, one single cycle
through that conversion sequence will be launched unless:
•
The BURST bit in the ADSEQn_CTRL register for this sequence is set to 1.
•
The requested conversion sequence is already in progress.
•
A set of conversions for the alternate conversion sequence is already in progress
except in the case of a B trigger interrupting an A sequence if the A sequence is set to
LOWPRIO.
If any of these conditions is true, the new trigger event will be ignored and will have no
effect.
In addition, if the single-step bit for a sequence is set, each new trigger will cause a single
conversion to be performed on the next channel in the sequence rather than launching a
pass through the entire sequence.
If the A sequence is enabled to be interrupted (i.e. the LOWPRIO bit in the SEQA_CTRL
register is set) and a B trigger occurs while an A sequence is in progress, then the
following will occur:
•
The A/D conversion which is currently in-progress will be aborted.
•
The A sequence will be paused, and the B sequence will immediately commence.
•
The interrupted A sequence will resume after the B sequence completes, beginning
with the conversion that was aborted when the interruption occurred. The channel for
that conversion will be re-sampled.
26.7.2.1 Avoiding spurious hardware triggers
Care should be taken to avoid generating a spurious trigger when writing to the
SEQn_CTRL register to change the trigger selected for the sequence, switch the polarity
of the selected trigger, or to enable the sequence for operation.
In general, the TRIGGER and TRIGPOL bits in the SEQn_CTRL register should only be
written to when the sequence is disabled (while the SEQn_ENA bit is LOW). The
SEQn_ENA bit itself should only be set when the selected trigger input is in its INACTIVE
