UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
454 of 515
NXP Semiconductors
UM11029
Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC)
26.6.5 A/D Channel Data Registers 0 to 11
The A/D Channel Data Registers hold the result of the last conversion completed for each
A/D channel. They also include status bits to indicate when a conversion has been
completed, when a data overrun has occurred, and where the most recent conversion fits
relative to the range dictated by the high and low threshold registers.
Results of A/D conversion can be read in one of two ways. One is to use the A/D Global
Data Registers for each of the sequences to read data from the ADC at the end of each
A/D conversion. Another is to use these individual A/D Channel Data Registers, typically
after the entire sequence has completed. It is recommended to use one method
consistently for a given conversion sequence.
Remark:
The method to be employed for each sequence should be reflected in the
MODE bit in the corresponding SEQ_CTRL register since this will impact interrupt and
overrun flag generation.
19:18
THCMPCROSS
Indicates whether the result of the last conversion performed represented a
crossing of the threshold level established by the designated LOW threshold
comparison register (THRn_LOW) and, if so, in what direction the crossing
occurred.
0x0 = No threshold Crossing detected:
The most recent completed conversion on this channel had the same relationship
(above or below) to the threshold value established by the designated LOW
threshold register (THRn_LOW) as did the previous conversion on this channel.
0x1 = Reserved.
0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing
in the downward direction has occurred - i.e. the previous sample on this channel
was above the threshold value established by the designated LOW threshold
register (THRn_LOW) and the current sample is below that threshold.
0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in
the upward direction has occurred - i.e. the previous sample on this channel was
below the threshold value established by the designated LOW threshold register
(THRn_LOW) and the current sample is above that threshold.
25:20
-
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
NA
29:26
CHN
These bits contain the channel from which the RESULT bits were converted (e.g.
0b0000 identifies channel 0, 0b0001 channel 1...).
NA
30
OVERRUN
This bit is set if a new conversion result is loaded into the RESULT field before a
previous result has been read - i.e. while the DATAVALID bit is set. This bit is
cleared, along with the DATAVALID bit, whenever this register is read.
This bit will contribute to an overrun interrupt request if the MODE bit (in
SEQB_CTRL) for the corresponding sequence is set to 0 (and if the overrun
interrupt is enabled).
0
31
DATAVALID
This bit is set to 1 at the end of each conversion when a new result is loaded into
the RESULT field. It is cleared whenever this register is read.
This bit will cause a conversion-complete interrupt for the corresponding sequence
if the MODE bit (in SEQB_CTRL) for that sequence is set to 0 (and if the interrupt is
enabled).
0
Table 447. A/D Sequence B Global Data Register (SEQB_GDAT, address 0x4001 C014) bit description
Bit
Symbol
Description
Reset
value
