UM11029
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© NXP B.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
24 of 515
NXP Semiconductors
UM11029
Chapter 5: LPC84x ISP and IAP
In case a CRP mode is enabled and access to the chip is allowed via the ISP, an
unsupported or restricted ISP command will be terminated with return code
CODE_READ_PROTECTION_ENABLED.
5.3.6.1 ISP entry protection
In addition to the three CRP modes, the user can prevent the sampling of the pin for
entering ISP mode and thereby release the pin for other applications. This is called the
NO_ISP mode. The NO_ISP mode can be entered by programming the pattern
0x4E69 7370 at location 0x0000 02FC.
The NO_ISP mode is identical to the CRP3 mode except for SWD access, which is
allowed in NO_ISP mode but disabled in CRP3 mode. The NO_ISP mode does not offer
any code protection.
5.3.6.2 ISP entry configuration and detection
The LPC84x UART/I2C/SPI ISP mode allows programming and reprogramming of the
internal FLASH via a set of commands on the UART, I2C slave, or SPI slave buses. Two
bits of the FAIM flash are used for ISP mode selection
.
Table 14.
USART ISP command limitations in CRP modes
Name
Pattern programmed
in 0x0000 02FC
Description
NO_ISP 0x4E69 7370
Prevents sampling of the pins for entering ISP mode. ISP sampling pin is available for
other applications.
CRP1
0x1234 5678
Access to chip via the SWD pins is disabled. This mode allows partial flash update using
the following USART ISP commands and restrictions:
•
Write to RAM command cannot access RAM below 0x1000 0600. Access to
addresses below 0x1000 0600 is disabled.
•
Copy RAM to flash command cannot write to Sector 0.
•
Erase command can erase Sector 0 only when all sectors are selected for erase.
•
Compare command is disabled.
•
Read Memory command is disabled.
This mode is useful when CRP is required and flash field updates are needed but all
sectors can not be erased. Since compare command is disabled in case of partial
updates the secondary loader should implement checksum mechanism to verify the
integrity of the flash.
CRP2
0x8765 4321
Access to chip via the SWD pins is disabled. The following ISP commands are disabled:
•
Read Memory
•
Write to RAM
•
Go
•
Copy RAM to flash
•
Compare
When CRP2 is enabled the ISP erase command only allows erasure of all user sectors.
CRP3
0x4321 8765
Access to chip via the SWD pins is disabled. ISP entry selected via the ISP entry pin is
disabled if a valid user code is present in flash sector 0.
This mode effectively disables ISP override using the entry pin. It is up to the application
of the user to provide a flash update mechanism using IAP calls or call reinvoke ISP
command to enable flash update via USART.
Caution: If CRP3 is selected, no future factory testing can be performed on the
device.