UM11029
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
500 of 515
NXP Semiconductors
UM11029
Chapter 32: Supplementary information
Table 314. Set Valid 0 register (SETVALID0, address 0x5000
8068) bit description . . . . . . . . . . . . . . . . . . . .276
Table 315. Set Trigger 0 register (SETTRIG0, address
0x5000 8070) bit description . . . . . . . . . . . . .276
Table 316. Abort 0 register (ABORT0, address 0x5000 8078)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .276
Table 317. Configuration registers for channel 0 to 24
(CFG[0:24], addresses 0x5000 8400 (CFG0) to
address 0x5000 8564 (CFG24)) bit description . .
277
Table 320. Transfer Configuration registers for channel 0 to
Table 321. USART pin description. . . . . . . . . . . . . . . . . .287
Table 322. Register overview: USART (base address
Table 323. USART Configuration register (CFG, address
Table 324. USART Control register (CTL, address 0x4006
Table 325. USART Status register (STAT, address 0x4006
Table 326. USART Interrupt Enable read and set register
Table 327. USART Interrupt Enable clear register
Table 328. USART Receiver Data register (RXDAT, address
Table 329. USART Receiver Data with Status register
Table 330. USART Transmitter Data Register (TXDAT,
Table 331. USART Baud Rate Generator register (BRG,
Table 332. USART Interrupt Status register (INTSTAT,
Table 333. USART Oversample selection register (OSR,
Table 334. USART Address register (ADDR, address
Table 335. SPI Pin Description . . . . . . . . . . . . . . . . . . . . 309
Table 336. Register overview: SPI (base address 0x4005
8000 (SPI0) and 0x4005 C000 (SPI1)) . . . . . 310
Table 337. SPI Configuration register (CFG, addresses
Table 338. SPI Delay register (DLY, addresses 0x4005 8004
(SPI0), 0x4005 C004 (SPI1)) bit description . 313
Table 339. SPI Status register (STAT, addresses 0x4005
8008 (SPI0), 0x4005 C008 (SPI1)) bit description
314
Table 340. SPI Interrupt Enable read and Set register
(INTENSET, addresses 0x4005 800C (SPI0),
0x4005 C00C (SPI1)) bit description . . . . . . . 315
Table 341. SPI Interrupt Enable clear register (INTENCLR,
Table 342. SPI Receiver Data register (RXDAT, addresses
Table 343. SPI Transmitter Data and Control register
(TXDATCTL, addresses 0x4005 8018 (SPI0),
0x4005 C018 (SPI1)) bit description . . . . . . . 318
Table 344. SPI Transmitter Data Register (TXDAT,
Table 345. SPI Transmitter Control register (TXCTL,
Table 346. SPI Divider register (DIV, addresses 0x4005 8024
(SPI0), 0x4005 C024 (SPI1)) bit description . 321
Table 347. SPI Interrupt Status register (INTSTAT, addresses