NXP Semiconductors LPC84x, Руководство пользователя

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User manual Rev. 1.0 — 16 June 2017 69 of 515
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Chapter 7: LPC84x Nested Vectored Interrupt Controller (NVIC)
7.4 Register description
The NVIC registers are located on the ARM private peripheral bus.
Table 109. Register overview: NVIC (base address 0xE000 E000)
Name Access Address
offset
Description Reset
value Reference
ISER0 RW 0x100 Interrupt Set Enable Register 0. This register allows enabling
interrupts and reading back the interrupt enables for specific
peripheral functions. 0 Table 110
- - 0x104 Reserved. - -
ICER0 RW 0x180 Interrupt Clear Enable Register 0. This register allows disabling
interrupts and reading back the interrupt enables for specific
peripheral functions. 0 Table 111
- - 0x184 Reserved. 0 -
ISPR0 RW 0x200 Interrupt Set Pending Register 0. This register allows changing the
interrupt state to pending and reading back the interrupt pending
state for specific peripheral functions. 0 Table 112
- - 0x204 Reserved. 0 -
ICPR0 RW 0x280 Interrupt Clear Pending Register 0. This register allows changing the
interrupt state to not pending and reading back the interrupt pending
state for specific peripheral functions. 0 Table 113
- - 0x284 Reserved. 0 -
IABR0 RO 0x300 Interrupt Active Bit Register 0. This register allows reading the
current interrupt active state for specific peripheral functions. 0 Table 114
- - 0x304 Reserved. 0 -
IPR0 RW 0x400 Interrupt Priority Registers 0. This register allows assigning a priority
to each interrupt. This register contains the 2-bit priority fields for
interrupts 0 to 3. 0 Table 115
IPR1 RW 0x404 Interrupt Priority Registers 1 This register allows assigning a priority
to each interrupt. This register contains the 2-bit priority fields for
interrupts 4 to 7. 0 Table 116
IPR2 RW 0x408 Interrupt Priority Registers 2. This register allows assigning a priority
to each interrupt. This register contains the 2-bit priority fields for
interrupts 8 to 11. 0 Table 117
IPR3 RW 0x40C Interrupt Priority Registers 3. This register allows assigning a priority
to each interrupt. This register contains the 2-bit priority fields for
interrupts 12 to 15. 0 Table 118
IPR4 RW 0x410 Interrupt Priority Registers 4. This register allows assigning a priority
to each interrupt. This register contains the 2-bit priority fields for
interrupts 16 to 19. 0 Table 119
IPR5 RW 0x414 Interrupt Priority Registers 5. This register allows assigning a priority
to each interrupt. This register contains the 2-bit priority fields for
interrupts 20 to 23. 0 Table 120
IPR6 RW 0x418 Interrupt Priority Registers 6. This register allows assigning a priority
to each interrupt. This register contains the 2-bit priority fields for
interrupts 24 to 27. 0 Table 121
IPR7 RW 0x41C Interrupt Priority Registers 7. This register allows assigning a priority
to each interrupt. This register contains the 2-bit priority fields for
interrupts 28 to 31. 0 Table 122