UM11029
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User manual
Rev. 1.0 — 16 June 2017
431 of 515
NXP Semiconductors
UM11029
Chapter 24: LPC84x Multi-Rate Timer (MRT)
24.6.2 Timer register
The timer register holds the current timer value. This register is read-only.
24.6.3 Control register
The control register configures the mode for each MRT and enables the interrupt.
Table 427. Time interval register (INTVAL[0:3], address 0x4000 4000 (INTVAL0) to 0x4000
4030 (INTVAL3)) bit description
Bit
Symbol Value
Description
Reset
value
30:0
IVALUE
Time interval load value. This value is loaded into the
TIMERn register and the MRTn starts counting down from
IVALUE -1.
If the timer is idle, writing a non-zero value to this bit field
starts the timer immediately.
If the timer is running, writing a zero to this bit field does the
following:
•
If LOAD = 1, the timer stops immediately.
•
If LOAD = 0, the timer stops at the end of the time
interval.
0
31
LOAD
Determines how the timer interval value IVALUE -1 is
loaded into the TIMERn register. This bit is write-only.
Reading this bit always returns 0.
0
0
No force load. The load from the INTVALn register to the
TIMERn register is processed at the end of the time interval
if the repeat mode is selected.
1
Force load. The INTVALn interval value IVALUE -1 is
immediately loaded into the TIMERn register while TIMERn
is running.
Table 428. Timer register (TIMER[0:3], address 0x4000 4004 (TIMER0) to 0x4000 4034
(TIMER3)) bit description
Bit
Symbol Description
Reset
value
30:0
VALUE
Holds the current timer value of the down counter. The initial value
of the TIMERn register is loaded as IVALUE - 1 from the INTVALn
register either at the end of the time interval or immediately in the
following cases:
INTVALn register is updated in the idle state.
INTVALn register is updated with LOAD = 1.
When the timer is in idle state, reading this bit fields returns -1
(0x00FF FFFF).
0x00FF
FFFF
31
-
Reserved.
0
