UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
349 of 515
NXP Semiconductors
UM11029
Chapter 19: LPC84x I2C0/1/2/3
The I2C clock pre-divider is described in
Table 361. Master Time register (MSTTIME, address 0x4005 0024 (I2C0), 0x4005 4024 (I2C1),
0x4003 0024 (I2C2), 0x4003 4024 (I2C3)) bit description
Bit
Symbol
Value Description
Reset
value
2:0
MSTSCLLOW
Master SCL Low time. Specifies the minimum low time
that will be asserted by this master on SCL. Other devices
on the bus (masters or slaves) could lengthen this time.
This corresponds to the parameter t
LOW
in the I
2
C bus
specification. I
2
C bus specification parameters t
BUF
and
t
SU;STA
have the same values and are also controlled by
MSTSCLLOW.
0x7
0x0
2 clocks. Minimum SCL low time is 2 clocks of the I
2
C
clock pre-divider.
0x1
3 clocks. Minimum SCL low time is 3 clocks of the I
2
C
clock pre-divider.
0x2
4 clocks. Minimum SCL low time is 4 clocks of the I
2
C
clock pre-divider.
0x3
5 clocks. Minimum SCL low time is 5 clocks of the I
2
C
clock pre-divider.
0x4
6 clocks. Minimum SCL low time is 6 clocks of the I
2
C
clock pre-divider.
0x5
7 clocks. Minimum SCL low time is 7 clocks of the I
2
C
clock pre-divider.
0x6
8 clocks. Minimum SCL low time is 8 clocks of the I
2
C
clock pre-divider.
0x7
9 clocks. Minimum SCL low time is 9 clocks of the I
2
C
clock pre-divider.
3
-
Reserved.
0
