UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
320 of 515
NXP Semiconductors
UM11029
Chapter 18: LPC84x SPI0/1
18.6.9 SPI Transmitter Control register
The TXCTL register provides a way to separately access control information for the SPI.
These bits are another view of the same-named bits in the TXDATCTL register (see
). Changing bits in TXCTL has no effect unless data is later written to the
TXDAT register. Data written to TXDATCTL overwrites the TXCTL register.
When control information needs to be changed during transmission, the TXDATCTL
register should be used (see
) instead of TXDAT. Control information can
then be written along with data.
18.6.10 SPI Divider register
The DIV register determines the clock used by the SPI in master mode.
For details on clocking, see
Section 18.7.3 “Clocking and data rates”
Table 344. SPI Transmitter Data Register (TXDAT, addresses 0x4005 801C (SPI0), 0x4005
C01C (SPI1)) bit description
Bit
Symbol
Description
Reset
value
15:0
DATA
Transmit Data. This field provides from 4 to 16 bits of data to be
transmitted.
0
31:16 -
Reserved. Only zero should be written.
NA
Table 345. SPI Transmitter Control register (TXCTL, addresses 0x4005 8020 (SPI0), 0x4005
C020 (SPI1)) bit description
Bit
Symbol
Description
Reset
value
15:0
-
Reserved. Read value is undefined, only zero should be
written.
NA
16
TXSSEL0_N
Transmit Slave Select 0.
0x0
17
TXSSEL1_N
Transmit Slave Select 1.
0x0
18
TXSSEL2_N
Transmit Slave Select 2.
0x0
19
TXSSEL3_n
Transmit Slave Select 3.
0x0
20
EOT
End of Transfer.
0
21
EOF
End of Frame.
0
22
RXIGNORE
Receive Ignore.
0
23
-
Reserved. Read value is undefined, only zero should be
written.
NA
27:24 LEN
Data transfer Length.
0x0
31:28 -
Reserved. Read value is undefined, only zero should be
written.
NA