NXP Semiconductors LPC84x, Руководство пользователя

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User manual Rev. 1.0 — 16 June 2017 318 of 515
NXP Semiconductors
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Chapter 18: LPC84x SPI0/1
18.6.7 SPI Transmitter Data and Control register
The TXDATCTL register provides a location where both transmit data and control
information can be written simultaneously. This allows detailed control of the SPI without a
separate write of control information for each piece of data, which can be especially useful
when the SPI is used with DMA.
Remark:
The SPI has no receiver control registers. Hence software needs to set the data
length in the transmitter control or transmitter data and control register first in order to
handle reception with correct data length. The programmed data length becomes active
only when data is actually transmitted. Therefore, this must be done before any data can
be received.
When control information remains static during transmit, the TXDAT register should be
used (see
Section 18.6.8 ) instead of the TXDATCTL register. Control information can then
be written separately via the TXCTL register (see Section 18.6.9 ). The upper part of
TXDATCTL (bits 27 to 16) are the same bits contained in the TXCTL register. The two
registers simply provide two ways to access them.
For details on the slave select process, see Section 18.7.4 .
For details on using multiple consecutive data transmits for transfer lengths larger than 16
bit, see
Section 18.7.6 “Data lengths greater than 16 bits” .
Table 343. SPI Transmitter Data and Control register (TXDATCTL, addresses 0x4005 8018 (SPI0), 0x4005 C018
(SPI1)) bit description
Bit Symbol Value Description Reset
value
15:0 TXDAT Transmit Data. This field provides from 1 to 16 bits of data to be transmitted. 0
16 TXSSEL0_N Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the
pin is active LOW by default.
Remark:
The active state of the SSEL0 pin is configured by bits in the CFG register.
0
0 SSEL0 asserted.
1 SSEL0 not asserted.
17 TXSSEL1_N Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the
pin is active LOW by default.
Remark:
The active state of the SSEL1 pin is configured by bits in the CFG register.
0
0 SSEL1 asserted.
1 SSEL1 not asserted.
18 TXSSEL2_N Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the
pin is active LOW by default.
Remark:
The active state of the SSEL2 pin is configured by bits in the CFG register.
0
0 SSEL2 asserted.
1 SSEL2 not asserted.
19 TXSSEL3_N Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the
pin is active LOW by default.
Remark:
The active state of the SSEL3 pin is configured by bits in the CFG register.
0
0 SSEL3 asserted.
1 SSEL3 not asserted.