UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
386 of 515
NXP Semiconductors
UM11029
Chapter 21: LPC84x SCTimer/PWM
21.6.3 SCTimer/PWM control register
If bit UNIFY = 1 in the CONFIG register, only the _L bits are used.
If bit UNIFY = 0 in the CONFIG register, this register can be written to as two registers
CTRL_L and CTRL_H. Both the L and H registers can be read or written individually or in
a single 32-bit read or write operation.
8
NORELOAD_H -
A 1 in this bit prevents the higher match registers from being reloaded from their
respective reload registers. Setting this bit eliminates the need to write to the
reload registers MATCHREL if the match values are fixed. Software can write to
set or clear this bit at any time. This bit is not used when the UNIFY bit is set.
0
12:9
INSYNC
-
Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 12 = input 3);
all other bits are reserved. A 1 in one of these bits subjects the corresponding
input to synchronization to the SCTimer/PWM clock, before it is used to create
an event. This synchronization injects a two SCT-clock delay in the input path.
Clearing this bit bypasses synchronization on the corresponding input.
This bit may be cleared for faster input response time if both of the following
conditions are met (for all Clock Modes):
The corresponding input is already synchronous to the SCTimer/PWM clock.
The SCTimer/PWM clock frequency does not exceed 100 MHz.
Note: The SCTimer/PWM clock is the bus/system clock for CKMODE 0-2 or the
selected, asynchronous input clock for CKMODE3.
Alternatively, for CKMODE2 only, it is also allowable to bypass synchronization
if both of the following conditions are met:
The corresponding input is synchronous to the designated CKMODE2 input
clock.
The CKMODE2 input clock frequency is less than one-third the frequency of
the bus/system clock.
1
16:13
-
-
Reserved.
-
17
AUTOLIMIT_L
-
This bit applies to the lower registers when the UNIFY bit = 0, and both the
higher and lower registers when the UNIFY bit is set. Software can write to set
or clear this bit at any time.
A one in this bit causes a match on match register 0 to be treated as a de-facto
LIMIT condition without the need to define an associated event.
As with any LIMIT event, this automatic limit causes the counter to be cleared to
zero in unidirectional mode or to change the direction of count in bi-directional
mode.
0
18
AUTOLIMIT_H
-
This bit applies to the upper registers when the UNIFY bit = 0, and is not used
when the UNIFY bit is set. Software can write to set or clear this bit at any time.
A one in this bit will cause a match on match register 0 to be treated as a
de-facto LIMIT condition without the need to define an associated event.
As with any LIMIT event, this automatic limit causes the counter to be cleared to
zero in unidirectional mode or to change the direction of count in bi-directional
mode.
0
31:19
-
-
Reserved
-
Table 386. SCTimer/PWM configuration register (CONFIG, offset 0x000) bit description
…continued
Bit
Symbol
Value
Description
Reset
value
