UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
5 of 515
NXP Semiconductors
UM11029
Chapter 1: LPC84x Introductory information
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Digital peripherals:
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High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to
32 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,
programmable open-drain mode, input inverter, and glitch filter. GPIO direction
control supports independent set/clear/toggle of individual bits.
–
High-current source output driver (20 mA) on four pins.
–
High-current sink driver (20 mA) on two true open-drain pins.
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GPIO interrupt generation capability with boolean pattern-matching feature on
eight GPIO inputs.
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Switch matrix for flexible configuration of each I/O pin function.
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CRC engine.
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DMA with 25 channels and 13 trigger inputs.
•
Timers:
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One SCTimer/PWM with five input and seven output functions (including capture
and match) for timing and PWM applications. Inputs and outputs can be routed to
or from external pins and internally to or from selected peripherals. Internally, the
SCTimer/PWM supports 8 match/captures, 8 events, and 8 states.
–
One 32-bit general purpose counter/timer, with four match outputs and three
capture inputs. Supports PWM mode, external count, and DMA.
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Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to
four programmable, fixed rates.
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Self-Wake-up Timer (WKT) clocked from either Free Running Oscillator (FRO), a
low-power, low-frequency internal oscillator, or an external clock input in the
always-on power domain.
–
Windowed Watchdog timer (WWDT).
•
Analog peripherals:
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One 12-bit ADC with up to 12 input channels with multiple internal and external
trigger inputs and with sample rates of up to 1.2 Msamples/s. The ADC supports
two independent conversion sequences.
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Comparator with five input pins and external or internal reference voltage.
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Two 10-bit DACs.
•
Serial peripherals:
–
Five USART interfaces with pin functions assigned through the switch matrix and
two fractional baud rate generators.
–
Two SPI controllers with pin functions assigned through the switch matrix.
–
Four I
2
C-bus interfaces. One I
2
C supports Fast-mode Plus with 1 Mbit/s data rates
on two true open-drain pins and listen mode. Three I
2
Cs support data rates up to
400 kbit/s on standard digital pins.
